Impact of on-chip process variations performance on MCML [MOS current mode logic]

Proceedings - IEEE International SOC Conference, SOCC 2003

Volumn , Issue , 2003, Pages 135-140

  Bruma, S ^a  

^a Philips EDT   (Netherlands)

Author keywords

Circuit noise; Coupling circuits; Crosstalk; Delay; Logic circuits; Noise generators; Noise reduction; Power dissipation; Power supplies; Voltage

Indexed keywords

COUPLED CIRCUITS; CROSSTALK; DELAY CIRCUITS; ELECTRIC LOSSES; ELECTRIC POTENTIAL; EMITTER COUPLED LOGIC CIRCUITS; ENERGY DISSIPATION; NOISE ABATEMENT; NOISE GENERATORS; PROGRAMMABLE LOGIC CONTROLLERS;

CIRCUIT NOISE; CLOSED-FORM EXPRESSION; DELAY; LOWER LIMITS; MOS CURRENT-MODE LOGIC; NOISE MARGINS; ON-CHIP PROCESS; POWER SUPPLY;

LOGIC CIRCUITS;

EID: 4944253891     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOC.2003.1241479     Document Type: Conference Paper

References (12)

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