Carbon nanotube electronics

IEEE Transactions on Nanotechnology

Volumn 1, Issue 4, 2002, Pages 184-188

  Appenzeller, Joerg ^a,b   Knoch, Joachim ^c,d   Martel, Richard ^b   Derycke, Vincent ^b   Wind, Shalom J ^a,b   Avouris, Phaedon ^b  

^a IEEE   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^d Massachusetts Institute of Technology   (United States)

Author keywords

Carbon nanotube; Field effect transistor (FET); Low dimensional system; Schottky barrier

Indexed keywords

CARBON NANOTUBE FIELD-EFFECT TRANSISTORS (CNFETS); LOW-DIMENSIONAL SYSTEM; SCHOTTKY BARRIER;

ELECTRIC POTENTIAL; ELECTRIC PROPERTIES; ELECTRODES; FIELD EFFECT TRANSISTORS; MOSFET DEVICES; SCHOTTKY BARRIER DIODES;

CARBON NANOTUBES;

EID: 1342279011     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2002.807390     Document Type: Conference Paper

References (31)

1. R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, and G. Dewey, "30-nm physical gate length CMOS transistor with 1.0-ps nMOS and 1.7-ps pMOS gate delays," in IEDM Tech. Dig., 2000, pp. 45-48.
2. H. Wakabayashi, M. Ueki, M. Narihiro, T. Fukai, N. Ikezawa, T. Matsuda, K. Yoshida, K. Takeuchi, Y. Ochiai, T. Mogami, and T. Kunio, "45-nm gate length CMOS technology and beyond using steep halo," in IEDM Tech. Dig., 2000, pp. 49-52.
3. J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T.-J. King, and C. Hu, "Complementary silicide source/drain thin-body MOSFETs for the 20-nm gate length regime," in IEDM Tech. Dig., 2000, pp. 57-60.
4. B. Yu, H. Wang, A. Joshi, Q. Xiang, E. Ibok, and M.-R. Lin, "15-nm gate length planar CMOS transistor," in IEDM Tech. Dig., 2001, pp. 937-939.
5. J. Appenzeller, R. Martel, P. Avouris, J. Knoch, J. A. del Alamo, P. Rice, and P. Solomon, "Sub-40-nm SOI V-groove nMOSFETs," IEEE Electron Device Lett., vol. 23, pp. 100-102, Feb. 2002.
6. D. J. Frank, R. H. Dennard, E. Nowak, P. M, Solomon, Y. Taur, and H.-S. P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies." Proc. IEEE, vol. 89, pp. 259-288, Mar. 2001.
7. F. Harris, Carbon Nanotubes and Related Structures. Cambridge, U.K.: Cambridge Univ. Press, 1999.
8. M. S. Dresselhaus, G. Dresselhaus, and P. Avouris, Eds., Carbon Nanotubes. Berlin, Germany: Springer-Verlag, 2001.
9. J. Appenzeller, H. Stahl, B. Lengeler, R. Martel, and P. Avouris, "Optimized contact configuration for the study of transport phenomena in ropes of single wall carbon nanotubes," Appl, Phys. Lett., vol. 78, pp. 3313-3315, 2001.
10. J. Hone, M. Whitney, C. Piscoti, and A. Zettl, "Thermal conductivity of single-waited carbon nanotubss," Phys. Rev. B, vol. 59, pp. R2514-R2516, 1999.
11. Z. Yao, C. L. Kane, and C. Dekker, "High-field electrical transport in single-wall carbon nanotubes," Phys. Rev. Lett., vol. 84, pp. 2941-2944, 2000.
12. S. J. Tans, A. Verschueren, and C. Dekker, "Room-temperature transistor based on a single carbon nznotube," Nature, vol. 393, pp. 49-51, 1998.
13. R. Martel, T. Schmidt, H. R. Shea, T. Hertel, and P. Avouris, "Single- and multi-wall carbon nanotube field-effect transistors," Appl. Phys. Lett., vol. 73, pp. 2447-2449, 1998.
14. H. T. Soh, C. F. Quate, A. F. Morpurgo, C. M. Marcus, J. Kong, and H. Dai, "Integrated nanotube circuits: Controlled growth and ohmic contacting of single-wall carbon nanotubes," Appl. Phys. Lett., vol. 75, pp. 627-629, 1999.
15. A. Bachtold, P. Hadley, T. Nakanishi, and C. Dekker, "Logic circuits with carbon nanotube transistors," Science, vol. 294, pp. 1317-1320, 2001.
16. S. Wind, J. Appenzeller, R. Martel, V. Derycke, and P. Avouris, "Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes," Appl. Phys. Lett., vol. 80. pp. 3817-3819, 2002.
17. V. Derycke, R. Martel, J. Appenzeller, and P. Avouris, "Carbon nanotube inter- and intramolecular logic gates," Nano Lett., vol. 1, pp. 453-456, 2001.
18. R. Martel, H.-S. P. Wong, K. Chan, and P. Avouris, "Carbon nanotube field-effect transistors for logic applications," in IEDM Tech. Dig., 2001, pp. 159-162.
19. C. Zhou, J. Kong, and H. Dai, "Electrical measurements of individual semiconducting single-walled carbon nanotubes of various diameters," Appl. Phys. Lett., vol. 76, pp. 1597-1599, 2000.
20. J. Appenzeller, J. Knoch, V. Derycke, R. Martel, S. Wind, and P. Avouris, "Field-modulated carrier transport in carbon nanotube transistors," Phys. Rev. Lett., vol. 89, pp. 126801-1-126801-4, 2002.
21. A. Thess, R. Lee, P. Nikolaev, H. Dai, P. Petit, J. Robert, C. Xu, Y. H. Lee, S. G. Kim, A. G. Rinzler, D. T. Colbert, G. E. Scuseria, D. Tomanek, J. E. Fischer, and R. E. Smalley, "Crystalline ropes of metallic carbon nanotubes," Science, vol. 273, pp. 483-487, 1996.
22. R. Martel, V. Derycke, C. Lavoie, J. Appenzeller, K. Chan, J. Tersoff, and P. Avouris, "Ambipolar electrical transport in semiconducting single-wall carbon nanotubes," Phys. Rev. Lett., vol. 87, pp. 256805-1-106801-4, 2001.
23. V. Derycke, R. Martel, J. Appenzeller, and P. Avouris, "Controlling doping and carrier injection in carbon nanotube transistors," Appl. Phys. Lett., vol. 80, pp. 2773-2775, 2002.
24. S. Heinze, J. Tersoff, R. Martel, V. Derycke, J. Appenzeller, and P. Avouris, "Carbon nanotubes as Schottky barrier transistors," Phys. Rev. Lett., vol. 89, pp. 106801-1-106801-4, 2002.
25. M. Freitag, M. Radosavljevic, Y. Zhou, and A. T. Johnson, "Controlled creation of a carbon nanotube diode by a scanned gate," Appl. Phys. Lett., vol. 79, pp. 3326-3328, 2001.
26. S. J. Tans and C. Dekker, "Potential modulations along carbon nanotubes," Nature, vol. 404, pp. 834-835, 2000.
27. 2/Si(100) for ultrashort channel Schottky barrier metal-oxide-semiconductor field effect transistors," Appl. Phys. Lett., vol. 74, pp. 454-456, 1999.
28. C. Wang, J. P. Snyder, and J. R. Tucker, "Sub-40 nm PtSi Schottky source/drain metal-oxide-semiconductor field-effect transistors," Appl. Phys. Lett., vol. 74, pp. 1174-1176, 1999.
29. J. Knoch and J. Appenzeller, "Impact of the channel thickness on the performance of Schottky barrier metal-oxide-semiconductor field-effect transistors," Appl. Phys. Lett., vol. 81, pp. 3082-3084, 2002.
30. G. D. J. Smit, S. Rogge, and T. M. Klapwijk, "Enhanced tunneling accross nanometer-scale metal-semiconductor interfaces," Appl. Phys. Lett., vol. 80, pp. 2568-2570, 2002.
31. M. S. Fuhrer, B. M. Kim, T. Duerkop, and T. Brintlinger, "High-mobility nanotube transistor memory," Nano Lett., vol. 2, pp. 755-759, 2002.