Construction of SEU tolerant flip-flops allowing enhanced scan delay fault testing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 9, 2010, Pages 1265-1276

  Namba, Kazuteru ^a   Ikeda, Takashi ^b   Ito, Hideo ^a  

^a CHIBA UNIVERSITY   (Japan)

^b Kawasaki Microelectronics Inc   (Japan)

Author keywords

Delay fault testing; enhanced scan testing; scan flip flop; single event upset (SEU); soft error tolerance

Indexed keywords

DELAY-FAULT TESTING; ENHANCED SCAN TESTING; SCAN FLIP-FLOPS; SINGLE EVENT UPSETS; SOFT-ERROR TOLERANCE;

ERROR CORRECTION; FAULT TOLERANCE; FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS; QUALITY ASSURANCE; SCANNING; STATIC RANDOM ACCESS STORAGE;

DELAY CIRCUITS;

EID: 77956228016     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2022083     Document Type: Article

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