A low power soft error suppression technique for dynamic logic

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2005, Pages 454-462

  Kumar, Jeetendra ^a   Tahoori, Mehdi B ^b  

^a ANALOG DEVICES INC   (United States)

^b NORTHEASTERN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY OVERHEAD; DYNAMIC LOGIC; SOFT-ERRORS; SUPPRESSION TECHNIQUE;

ENERGY UTILIZATION; ERROR DETECTION; LOGIC GATES; TRANSISTORS;

LOGIC DEVICES;

EID: 28444454859     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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