Design technique for mitigation of alpha-particle-induced single-event transients in combinational logic

IEEE Transactions on Device and Materials Reliability

Volumn 3, Issue 3, 2003, Pages 89-92

  Mongkolkachit, Pitsini ^a   Bhuva, Bharat ^a  

^a VANDERBILT UNIVERSITY   (United States)

Author keywords

CMOS; Integrated circuit design; Single event upsets

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DATA REDUCTION; ELECTRONICS PACKAGING; ERROR ANALYSIS; OPTIMIZATION; TRANSIENTS;

COMBINATIONAL LOGIC; INTEGRATED CIRCUIT DESIGN; SINGLE-EVENT UPSETS;

ALPHA PARTICLES;

EID: 3042783438     PISSN: 15304388     EISSN: None     Source Type: Journal    
DOI: 10.1109/TDMR.2003.816568     Document Type: Article

References (6)

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6. M. Satagopan, "Modeling of SEU Effects on Combinational Circuits," M.S. thesis, Vanderbilt Univ., Nashville, TN, 1994.