Time-domain modeling of an RF all-digital PLL

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 55, Issue 6, 2008, Pages 601-605

  Syllaios, Ioannis L ^a   Staszewski, Robert Bogdan ^b   Balsara, Poras T ^a  

^a UNIVERSITY OF TEXAS AT DALLAS   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

All digital phase locked loop (ADPLL); CMOS; Digitally controlled oscillator (DCO); Event driven; GSM; Mobile phones; Phase detection; Phase noise; Simulation; Time domain modeling; Time to digital converter (TDC); Wireless

Indexed keywords

CELLULAR TELEPHONES; CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION LANGUAGES; FREQUENCY CONVERTERS; GLOBAL SYSTEM FOR MOBILE COMMUNICATIONS; MATLAB; MODELING LANGUAGES; PHASE LOCKED LOOPS; PHASE NOISE; RADIO;

ALL DIGITAL PHASE LOCKED LOOP; DIGITALLY CONTROLLED OSCILLATORS; EVENT-DRIVEN; PHASE DETECTION; SIMULATION; TIME DOMAIN MODELING; TIME TO DIGITAL CONVERTERS;

TIME DOMAIN ANALYSIS;

EID: 46649102037     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2007.916845     Document Type: Article

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