A low-overhead asynchronous interconnection network for GALS chip multiprocessors

NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip

Volumn , Issue , 2010, Pages 43-50

  Horak, Michael N ^a   Nowick, Steven M ^b   Carlberg, Matthew ^c   Vishkin, Uzi ^a  

^a UNIVERSITY OF MARYLAND   (United States)

^b Department of Earth and Environmental Sciences   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

90 NM TECHNOLOGY; ASYNCHRONOUS COMPONENTS; CAN INTERFACE; CHIP MULTIPROCESSOR; CLOCK RATE; GLOBAL CLOCKS; GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS; OPERATING RANGES; PARALLEL BENCHMARKS; POST LAYOUT SIMULATION; SHARED-MEMORY PARALLELS; TRAFFIC RATE;

INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; PARALLEL ARCHITECTURES; TIME MEASUREMENT;

ROUTERS;

EID: 77955101700     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2010.14     Document Type: Conference Paper

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