An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 435-440

  Balkan, Aydin O ^a   Qu, Gang ^a   Vishkin, Uzi ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

Hybrid networks; Mesh of Trees; On chip networks

Indexed keywords

HIGH THROUGHPUTS; HYBRID NETWORKS; MESH-OF-TREES; ON-CHIP NETWORKS; PARALLEL PROCESSING;

COMPUTER AIDED DESIGN; COMPUTER NETWORKS; DIGITAL INTEGRATED CIRCUITS; INDUSTRIAL ENGINEERING; THROUGHPUT;

DATA STORAGE EQUIPMENT;

EID: 51549119170     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555857     Document Type: Conference Paper

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