Practical asynchronous interconnect network design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 5, 2008, Pages 579-588

  Quinton, Bradley R ^a,b   Greenstreet, Mark R ^a,b   Wilton, Steven J E ^a,b  

^a IEEE

^b UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

Asynchronous logic circuits; Design automation; Interconnection networks; Network on chip (NoC); System on chip (SoC)

Indexed keywords

AUTOMATION; COMPUTER AIDED DESIGN; EMBEDDED SYSTEMS; LOGIC CIRCUITS; TREES (MATHEMATICS);

ASYNCHRONOUS LOGIC CIRCUITS; DESIGN AUTOMATION; NETWORK-ON-CHIP (NOC); SYSTEM-ON-CHIP (SOC);

INTERCONNECTION NETWORKS;

EID: 42649133492     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.917545     Document Type: Article

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