RasP: An area-efficient, on-chip network

IEEE International Conference on Computer Design, ICCD 2006

Volumn , Issue , 2006, Pages 63-69

  Hollis, Simon ^a   Moore, Simon W ^a  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK TOPOLOGY;

1 GBIT/S; COMPUTER DESIGNS; HIGH SPEEDS; INTERNATIONAL CONFERENCES; LINK BANDWIDTHS; NOISE RATIOS; ON-CHIP NETWORK; POINT-TO-POINT LINK; SKEW TOLERANCE; SYSTEM DESIGNERS;

SIGNAL TO NOISE RATIO;

EID: 49749088945     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2006.4380795     Document Type: Conference Paper

References (16)

1. R. Ho, "On-chip wires: Scaling and efficiency," Ph.D. dissertation, Department of Electrical Engineering, Stanford Universiy, Aug 2003.
2. I. Sutherland and S. Fairbanks, "GasP: A minimal FIFO control," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, Mar. 2001, pp. 46-53.
3. J. Sparsø and S. Furber, Eds., Principles of Asyncronous Circuit Design: A Systems Perspective. Kluwer Academic Publishers, Boston, 2001.
4. I. E. Sutherland, "Micropipelines (the Turing award lecture)." Comm. A.C.M., vol. 32, no. 6, pp. 720-738, June 1989.
5. M. Ferretti and P. Beerel, "Single-track asynchronous pipeline templates using 1-of-n encoding," in Proc. Design, Automation and Test in Europe (DATE). 2002.
6. T. Nanya and Y. Kameda, "Pulse-driven delay-insensitive circuits us-ing single-flux-quantum devices," in Proc. International Conference of Computer Design, 1996.
7. R. Ho, J. Gainsley, and R. Drost, "Long wires and asynchronous control," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, Apr. 2004, pp. 240-249.
8. S. Hollis and S. W. Moore, "An area-efficient, pulse-based interconnect," in Proc. International Symposium on Circuits and Systems (ISCAS), May 2006.
9. Magma Design Automation Ltd., "Quickcap." [Online], Available: http://www.magma-da.com
10. Synopsis(R), "hspice." [Online], Available: http://www.synopsys.com/products/mixedsignal/hspice/hspice.html
11. H. Johnson and M. Graham, High-speed Digital Design: A Handbook of Black Magic. Prentice Hall, 1993.
12. A. S. Tanenbaum, Computer Networks. Prentice Hall, 1981.
13. Y. I. Ismail and E. G. Friedman, "Repeater insertion in RLC lines for minimum propagation delay," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS). May 1999
14. R. J. Tocci, Digital Systems: Principles & Applications, 6th Edition. Prentice Hall, 1995.
15. N. H. Weste and D. Harris, CMOS VLSI Design (Third Edition). Wesley, 2005.
16. J. Bainbridge and S. Furber, "CHAIN: A delay-insensitive chip area interconnect," IEEE Micro, vol. 22, pp. 16-23, 2002.