Time-to-digital converter with vernier delay mismatch compensation for high resolution on-die clock jitter measurement

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 166-167

  Hashimoto, Tetsutaro ^a   Yamazaki, Hirotaka ^a   Muramatsu, Atsushi ^a   Sato, Tomio ^a   Inoue, Atsuki ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

On chip jitter measurement; On die jitter measurement; Time to digital converter; Vernier delay line

Indexed keywords

TIMING JITTER; VLSI CIRCUITS;

DELAY MISMATCH; HIGH RESOLUTION; ON-CHIP JITTER MEASUREMENT; ON-DIE JITTER MEASUREMENT; OSCILLATION MEASUREMENTS; TIME TO DIGITAL CONVERTERS; TIMING RESOLUTIONS; VERNIER DELAY LINE;

FREQUENCY CONVERTERS;

EID: 51949109964     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4585992     Document Type: Conference Paper

References (4)

1. M. S. Gorbics, J. Kelly, K. M. Roberts, R. L. Sumner, "A High Resolution Multihit Time to Digital Converter Integrated Circuit," IEEE Trans. on Nuclear Science, Vol. 44, No. 3, Jun. 1997.
2. P. Dudek, S. Szczepanski, J. V. Hatfield, "A High-Resolution CMOS Time -to-Digital Converter Utilizing a Vernier Delay Line," IEEE Trans. on Solid-State Circuits, Vol. 35, No. 2, Feb. 2000.
3. A. H. Chan, G. W. Roberts, "A Jitter Characterization System Using a Component-Invariant Vernier Delay Line," IEEE Trans. on VLSI Systems, Vol. 12, No. 1, Jan. 2004.
4. K. Nose, M. Kajita, M. Mizuno, "A 1ps-Resolution Jitter Measurement Macro Using Interpolated Jitter Oversampling," IEEE ISSCC, pp. 520-521, 2006.