Discrete buffer and wire sizing for link-based non-tree clock networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 7, 2010, Pages 1025-1035

  Samanta, Rupak ^a   Hu, Jiang ^b   Li, Peng ^b  

^a INTEL CORPORATION   (United States)

^b Department of Electrical and Computer Engineering   (United States)

Author keywords

Clock; discrete; links; non tree; sizing; support vector machine (SVM)

Indexed keywords

ACCURATE DELAY MODELS; BENCHMARK CIRCUIT; CIRCUIT-LEVEL SIMULATION; CLOCK NETWORK; CLOCK SKEWS; DISCRETE; HYBRID OPTIMIZATION; MACHINE-LEARNING; NON-TREE CLOCKS; POWER CONSUMERS; POWER DISSIPATION; POWER OVERHEAD; TWO STAGE; VARIATION TOLERANCES; WIRE SIZING;

NETWORKS (CIRCUITS); OPTIMIZATION; SUPPORT VECTOR MACHINES; WIRE;

ELECTRIC CLOCKS;

EID: 77954087158     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2019088     Document Type: Article

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