Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 2, 1997, Pages 210-215

  Pullela, Satyamurthy ^a,b   Menezes, Noel ^a,b   Pileggi, Lawrence T ^a,b  

^a MOTOROLA INC   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Clock; Optimization; Synthesis; Wiring

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; ELECTRIC NETWORK SYNTHESIS; HEURISTIC METHODS; INTEGRATED CIRCUITS; OPTIMIZATION;

ELMORE DELAY MODEL; MOMENT SENSITIVITY BASED METHODS; SKEW REDUCTION;

TIMING CIRCUITS;

EID: 0031074190     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.573836     Document Type: Article

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