Fast incremental link insertion in clock networks for skew variability reduction

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2006, Pages 79-84

  Rajaram, Anand ^a,b   Pan, David Z ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK NETWORK; EMPIRICAL PARAMETERS; LINK INSERTIONS; SKEW REDUCTION; SPICE-BASED; STATISTICAL LINKS; VARIABILITY REDUCTION; VLSI TECHNOLOGY;

CLOCK DISTRIBUTION NETWORKS; FORESTRY; MONTE CARLO METHODS;

CLOCKS;

EID: 84886743533     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.66     Document Type: Conference Paper

References (10)

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10. http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/BST/