Statistical based link insertion for robust clock network design

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 588-591

  Lam, W C D ^a   Jain, J ^a   Koh, C K ^a   Balakrishnan, V ^a   Chen, Yiran ^b  

^a PURDUE UNIVERSITY   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; COMPUTER AIDED DESIGN; MONTE CARLO METHODS; ROBUSTNESS (CONTROL SYSTEMS); STATISTICAL METHODS;

LINK INSERTION; ROBUST CLOCK NETWORK DESIGN; SKEW VARIATION; WIRE WIDTH;

COMPUTER NETWORKS;

EID: 33751423844     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560134     Document Type: Conference Paper

References (18)

1. Arif Ishaq Abou-Seido, Brian Nowak, and Chris Chu. Fitted elmore delay: a simple and accurate interconnect delay model. IEEE Trans. Very Large Scale Integr. Syst., 12(7):691-696, 2004.
2. A. Agarwal, D. Blaauw, and V. Zolotov. Statistical timing analysis for intra-die process variations with spatial correlations. In Proc. Int. Conf. on Computer Aided Design, pages 900-907, 2003.
3. K. D. Boese, A. B. Kahng, B. A. McCoy, and G. Robins. Fidelity and near-optimality of Elmore-based routing constructions. In Proc. IEEE Int. Conf. on Computer Design, pages 81-84, 1993.
4. P. K. Chan and K. Karplus. Computing signal delay in general re networks by tree/link partitioning. In DAC '89: Proceedings of the 26th ACM/IEEE conference on Design automation, pages 485-490. ACM Press, 1989.
5. H. Chang and S. Sapatnekar. Statistical timing analysis considering spatial correlations using a single pert-like traversal. In Proc. Design Automation Conf, 2003.
6. J. P. Fishburn. Clock skew optimization. IEEE Trans. on Computers, 39(7):945-951, July 1990.
7. G. H. Golub and C. F. van Loan. Matrix Computations. The Johns Hopkins University Press, Baltimore, Maryland, third edition edition, 1996.
8. R. Gupta, B. Tutuianu, B. Krauter, and L. T. Pillage. The Elmore delay as a bound for RC trees with generalized input signals. In Proc. Design Automation Conf, pages 364-369, June 1995.
9. J. Jain, Koh C.-K., and V. Balakrishnan. Fast simulation of vlsi interconnects. In Proc. Int. Conf. on Computer Aided Design, pages 93-98, 2004.
10. S. Lin and C. K. Wong. Process-variation-tolerant clock skew minimization. In Proc. Int. Conf. on Computer Aided Design, pages 284-288, 1994.
11. Y. Liu, S. Nassif, L. Pileggi, and A. Strojwas. Impact of interconnect variations on the clock skew of a gigahertz microprocessor. In Proc. Design Automation Conf, 2000.
12. D. F. Morrison. Multivariate Statistical Methods. New York: McGraw-Hill, 1976.
13. S. Pullela, N. Menezes, and L. T. Pillage. Reliable non-zero skew clock trees using wire width optimization. In Proceedings of the 30th international conference on Design automation, pages 165-170. ACM Press, 1993.
14. A. Rajaram, J. Hu, and R. Mahapatra. Reducing clock skew variability via cross links. In Proceedings of the 41st annual conference on Design automation, pages 18-23. ACM Press, 2004.
15. P.J. Restle, T.G. McNamara, D.A. Webber, P.J. Camporese, K.F. Eng, K.A. Jenkins, D.H. Allen, M.J. Rohnand, M.P. Quaranta, D.W. Boerstler, C.J. Alpert, C.A. Carter, R.N. Bailey, J.G. Petrovick, B.L. Krauter, and B.D. McCredie. A clock distribution network for microprocessors. In IEEE Journal of Solid-State Circuits, volume 36 (5), pages 792-799, May 2001.
16. H. Su and S. Sapatnekar. Hybrid structured clock network construction. In Proc. Int. Conf. on Computer Aided Design, pages 333-336, 2001.
17. C.-W A. Tsao and C.-K. Koh. UST/DME: A clock tree router for general skew constraints. ACM (TODAES), 7:359-379, 2002.
18. D. Velenis, E. Friedman, and M. Papaefthymiou. A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. In Proc. IEEE Int. Symp. on Circuits and Systems, pages 4.422-4.425, May 2001.