General skew constrained clock network sizing based on sequential linear programming

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 5, 2005, Pages 773-781

  Wang, Kai ^a   Ran, Yajun ^a   Jiang, Hailin ^a   Marek Sadowska, Malgorzata ^a  

^a University of California   (United States)

Author keywords

Clock slew; Power supply noise; Sequential linear programming

Indexed keywords

BUFFER CIRCUITS; COMPUTER SIMULATION; ELECTRIC CLOCKS; FORMAL LOGIC; LINEAR PROGRAMMING; MICROPROCESSOR CHIPS; SYNCHRONIZATION;

CLOCK SLEW; POWER SUPPLY NOISE; SEQUENTIAL LINEAR PROGRAMMING; USEFUL SKEW TREE (UST);

INTEGRATED CIRCUIT LAYOUT;

EID: 18744393477     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.846362     Document Type: Article

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