Practical techniques to reduce skew and its variations in buffered clock networks

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 592-596

  Venkataraman, Ganesh ^a   Jayakumar, Nikhil ^a   Hu, Jiang ^a   Li, Peng ^a   Khatri, Sunil ^a   Rajaram, Anand ^b   McGuinness, Patrick ^c   Alpert, Charles ^d  

^a TEXAS A AND M UNIVERSITY   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c FREESCALE SEMICONDUCTOR INC   (United States)

^d IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTATIONAL METHODS; COMPUTER AIDED DESIGN; COST EFFECTIVENESS; MONTE CARLO METHODS;

BUFFERED CLOCK NETWORKS; CLOCK SKEW VARIATIONS; SHORT CIRCUIT RISK; SPATIAL CORRELATIONS;

COMPUTER NETWORKS;

EID: 33751426660     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560135     Document Type: Conference Paper

References (19)

1. N. A. Kurd, J. S. Barkatullah, R. O. Dizon, T. D. Fletcher, and P. D. Madland. A multigigahertz clocking scheme for the Pentium 4 microprocessor. IEEE Journal of Solid-State Circuits, 36(11):1647-1653, November 2001.
2. P. J. Restle, T. G. McNamara, D. A. Webber, P. J. Camporese, K. F. Eng, K. A. Jenkins, D. H. Allen, M. J. Rohn, M. P. Quaranta, D. W. Boerstler, C. J. Alpert, C. A. Carter, R. N. Bailey, J. G. Petrovick, B. L. Krauter, and B. D. McCredie. A clock distribution network for microprocessors. IEEE Journal of Solid-State Circuits, 36(5):792-799, May 2001.
3. N. Bindal, T. Kelly, N. Velastegui, and K. L. Wong. Scalable sub-10ps skew global clock distribution for a 90nm multi-GHz IA microprocessor. In Proceedings of the IEEE International Solid-State Circuits Conference, pages 346-355, 2003.
4. A. Rajaram, J. Hu, and R. Mahapatra. Reducing clock skew variability via cross links. In Proceedings of the ACM/IEEE Design Automation Conference, pages 18-23, 2004.
5. A. Rajaram, D. Pan, and J. Hu. Improved algorithms for link based non-tree clock network for skew variability reduction. In Proceedings of the ACM International Symposium on Physical Design, pages 55-62, 2005.
6. X. Jiang and S. Horiguchi. Statistical skew modeling for general clock distribution networks in presence of process variations. IEEE Transactions on VLSI Systems, 9(5):704-717, October 2001.
7. J. Rubinstein, P. Penfield, and M. A. Horowitz. Signal delay in RC tree networks. IEEE Transactions on Computer-Aided Design, CAD-2(3):202-211, July 1983.
8. T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng. Zero skew clock routing with minimum wirelength. IEEE Transactions on Circuits and Systems - Analog and Digital Signal Processing, 39(11):799-814, November 1992.
9. M. Edahiro. A clustering-based optimization algorithm in zero-skew routings. In Proceedings of the ACM/IEEE Design Automation Conference, pages 612-616, 1993.
10. S. Pullela, N. Menezes, J. Omar, and L. T. Pillage. Skew and delay optimization for reliable buffered clock trees. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pages 556-562, 1993.
11. J. G. Xi and W. W.-M. Dai. Buffer insertion and sizing under process variations for low power clock distribution. In Proceedings of the ACM/IEEE Design Automation Conference, pages 491-496, 1995.
12. R. Chaturvedi and J. Hu. Buffered clock tree for high quality IC design. In Proceedings of the IEEE International Symposium on Quality Electronic Design, pages 381-386, 2004.
13. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. L. Sangiovanni- Vincentelli. SIS: a system for sequential circuit synthesis. Memorandum no. M92/41, ERL, University of California, Berkeley, May 1992.
14. CPMO-constrained placement by multilevel optimization. http://ballade.cs.ucla.edu/cpmo/. Computer Science Department, UCLA.
15. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu. New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation. In Proceedings of the IEEE Custom Integrated Circuits Conference, pages 201-204, 2000.
16. SPACE: VLSI physical design modeling and verification. http://space.tudelft.nl. Delft University of Technology in the Netherlands.
17. S. P. Khatri, A. Mehrotra, R. K. Brayton, A. Sangiovanni-Vincentelli, and R. H. J. M. Otten. A novel VLSI layout fabric for deep sub-micron applications. In Proceedings of the ACM/IEEE Design Automation Conference, pages 491-496, 1999.
18. J. L. Tsai, D. Baik, C. C. Chen and K. Saluja A yield improvement methodology using pre- and post-silicon statistical clock scheduling In Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2004.
19. H. Chang and S. S. Sapatnekar. Statistical timing analysis considering spatial correlations using a single PERT-like traversal. In Proceedings of the IEEE/ACM Int Conference on Comp. Aided Design, pages 621-625, 2003.