ε-Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2003, Pages 166-173

  Tsai, Jeng Liang ^a   Chen, Tsung Hao ^a   Chen, Charlie Chung Ping ^b  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

optimal; Clock tree; Incremental refinement; Pseudo polynomial; Wire sizing; Zero skew

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; POLYNOMIALS; TREES (MATHEMATICS);

INCREMENTAL REFINING;

VLSI CIRCUITS;

EID: 0038716746     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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