Clock buffer and wire sizing using sequential programming

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 1041-1046

  Guthaus, Matthew R ^a   Sylvester, Dennis ^a   Brown, Richard B ^b  

^a The Department of Civil and Environmental Engineering   (United States)

^b University of Utah   (United States)

Author keywords

Clock tree synthesis; Robust design; Skew

Indexed keywords

BUFFER CIRCUITS; COMPUTER SIMULATION; ELECTRIC WIRE; MONTE CARLO METHODS; OPTIMIZATION; QUADRATIC PROGRAMMING;

CLOCK TREE SYNTHESIS; ROBUST DESIGN; SEQUENTIAL PROGRAMMING; SKEW;

ELECTRIC CLOCKS;

EID: 34547181982     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147171     Document Type: Conference Paper

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