Variation tolerant buffered clock network synthesis with cross links

Proceedings of the International Symposium on Physical Design

Volumn 2006, Issue , 2006, Pages 157-164

  Rajaram, Anand ^a,b   Pan, David Z ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

Clock Network; Non tree Clocks; Physical Design; VLSI CAD

Indexed keywords

ALGORITHMS; ELECTRIC POTENTIAL; PROBLEM SOLVING; PROCESS CONTROL; THERMAL EFFECTS;

CLOCK NETWORK; NON-TREE CLOCKS; PHYSICAL DESIGN; VLSI CAD;

ELECTRIC NETWORK ANALYSIS;

EID: 33745946821     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1123008.1123038     Document Type: Conference Paper

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