A two-cycle lock-in time ADPLL design based on a frequency estimation algorithm

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 57, Issue 6, 2010, Pages 430-434

  Wu, Chia Tsun ^a   Shen, Wen Chung ^a   Wang, Wei ^a   Wu, An Yeu ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

All digital phase locked loop (ADPLL); binary search algorithm (BSA); clock generator; digitally controlled oscillator (DCO); phase locked loop (PLL)

Indexed keywords

CLOCKS; LOCKS (FASTENERS); MICROELECTRONICS; PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

ALL DIGITAL PHASE LOCKED LOOP; BINARY SEARCH ALGORITHM; CLOCK GENERATOR; DIGITALLY CONTROLLED OSCILLATORS; PHASE LOCKED LOOP (PLL);

FREQUENCY ESTIMATION;

EID: 77953727164     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2010.2048358     Document Type: Article

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