A digitally controlled oscillator for low jitter all digital phase locked loops

2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Volumn , Issue , 2005, Pages 365-368

  Lee, Kwang Jin ^a   Jung, Seung Hun ^a   Kim, Yun Jeong ^a   Kim, Chul ^a   Kim, Suki ^a   Cho, Uk Rae ^b   Kwak, Choong Guen ^b   Byun, Hyun Geun ^b  

^a Korea University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; JITTER; MICROPROCESSOR CHIPS; OSCILLATORS (ELECTRONIC); THERMOMETERS;

DCO CIRCUITS; DIGITALLY CONTROLLED OSCILLATORS; HIGH SPEED ADPLLS;

PHASE LOCKED LOOPS;

EID: 34250711786     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2005.251741     Document Type: Conference Paper

References (5)

1. Cangsang Zhao and Uddalak Bhattacharya, "An 18-Mb, 12.3 GB/s CMOS Pipeline-Burst Cache SRAM with 1.54 Gb/s/pin", IEEE J. Solid-State Circuits, Vol. 34, pp. 1564-1570, Nov. 1999
2. Kwang-Jin Lee et al, "Voltage-Mode 1.5 Gbps Interface Circuits for Chip-to-Chip Communication", ETRI Journal, Vol 27, No.1, pp.81-88, Feb. 2005
3. J. Dunning et al., "An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High Performance Microprocessors", IEEE J. Solid State Circuits, Vol. 30, pp. 312-422, April.1995
4. Ching-Che Chung et al, "An All-Digital Phase-Locked Loop for High-Speed Clock Generation", IEEE J. Solid State circuits, vol.38, pp. 347-351, Feb. 2003
5. M. Saint-Laurent et al, "A Digitally Controlled Oscillator Constructed Using Adjustable Resistor", IEEE Southwest Symposium on Mixed-Signal Design,2001