A scalable DCO design for portable ADPLL designs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 5449-5452

  Wu, Chia Tsun ^a   Wang, Wei ^a   Wey, I Chyn ^a   Wu, An Yeu ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN EFFORT; DESIGN FLOWS; DESIGN METHODOLOGY; HIGH PERFORMANCE CLOCKS; HIGH RESOLUTION; NEW DESIGN; OPERATING RANGES; PRECISE ANALYSIS; SYSTEM-ON-A-CHIP APPLICATIONS;

DESIGN;

ARCHITECTURAL DESIGN;

EID: 48049096467     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465869     Document Type: Conference Paper

References (8)

1. J. Jong and C. Lee, "A novel structure for portable digitally controlled oscillator," IEEE International Symposium on Circuits and Systems, vol.1, pp.272 - 275, May 2001.
2. C.Chung and C. Lee, "An all-digital phase-locked loop for highspeed clock generation," IEEE International Symposium on Circuits and Systems, vol. 3, pp.26-29, May 2002.
3. T. Hsu, B. Shieh and C. Lee, "An all-digital phase-locked loop (ADPLL)-based clock recovery circuit," IEEE Journal of Solid-State Circuits, vol. 34, pp.1063-1073, Aug 1999.
4. J. Chiang and K. Chen, "A 3.3 V all digital phase-locked loop with small DCO hardware and fast phase lock," IEEE International Symposium on Circuits and Systems, vol. 3, pp.554-557, May 1998.
5. Pialis and K. Phang, "Analysis of Timing Jitter in Ring Oscillators Due to Power Supply Noise," IEEE International Symposium on Circuits and Systems, vol. 1, pp.I-685 - I-688, May 2003.
6. A. Abidi and R. G. Meyer, "Noise in Relaxation Oscillators," IEEE Journal of Solid-State Circuits, Vol. 18, pp.794-802, December 1983.
7. T. Olsson and P. Nilsson, "A digitally controlled PLL for SoC applications," IEEE Journal of Solid-State Circuits, vol. 39, pp.751-760, May 2004.
8. Zhinian Shu; Ka Lok Lee; Leung, B.H.," 2.4-GHz ring-oscillatorbased CMOS frequency synthesizer with a fractional divider dual-PLL architecture," IEEE Journal of Solid-State Circuits, vol:39, pp.452-462, March 2004.