A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 3, 2004, Pages 452-462

  Shu, Zhinian ^a   Lee, Ka Lok ^b   Leung, Bosco H ^c  

^a Synopsys Mix Signal IP Group   (Canada)

^b Sirific Wireless Corporation   (Canada)

^c UNIVERSITY OF WATERLOO   (Canada)

Author keywords

Frequency synthesizer; Jitter; Phase noise; Phase locked loop (PLL); Ring oscillator; Spurs

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL FILTERS; ELECTRIC POWER SUPPLIES TO APPARATUS; FREQUENCY DIVIDING CIRCUITS; INTERFERENCE SUPPRESSION; JITTER; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; VARIABLE FREQUENCY OSCILLATORS;

FRACTIONAL DIVIDER ARCHITECTURE; ON CHIP RING OSCILLATOR; PHASE NOISE;

FREQUENCY SYNTHESIZERS;

EID: 1542500872     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.822896     Document Type: Article

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