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IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 52, Issue 5, 2005, Pages 233-237

A Portable Digitally Controlled Oscillator Using Novel Varactors

(3) Chen, Pao Lung a Chung, Ching Che a Lee, Chen Yi a

a NATIONAL CHIAO TUNG UNIVERSITY (Taiwan)

Author keywords

All digital phase locked loop (ADPLL); cell based hardware description language; digitally controlled oscillator (DCO); digitally controlled varactor (DCV); PLL

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; LINEAR EQUATIONS; LOGIC GATES; PHASE LOCKED LOOPS; VARACTORS;

ALL DIGITAL PHASE LOCKED LOOP (ADPLL); CELL BASED HARDWARE DESCRIPTION LANGUAGE; DIGITALLY CONTROLLED OSCILLATOR (DCO); DIGITALLY CONTROLLED VARACTOR (DCV);

OSCILLATORS (ELECTRONIC);

EID: 20444385790 PISSN: 15497747 EISSN: 15583791 Source Type: Journal
DOI: 10.1109/TCSII.2005.846307 Document Type: Article

Times cited : (95)

References (7)

1
- 0344512371
- Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process
- Nov.
- R. B. Staszewski, D. Leipold, K. Muhammand, and P. T. Balsara, “Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 11, pp. 815–822, Nov. 2003.
- (2003) IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. , vol.50 , Issue.11 , pp. 815-822
- Staszewski, R.B.¹ Leipold, D.² Muhammand, K.³ Balsara, P.T.⁴

2
- 2442649398
- A PVT tolerant 0.18 MHz to 600 MHz self-calibrated digital PLL in 90 nm CMOS process
- Feb.
- J. Lin, B. Haroun, T. Foo, J.-S. Wang, B. Helmick, S. Randall, T. Mayhugh, C. Barr, and J. Kirkpartick, “A PVT tolerant 0.18 MHz to 600 MHz self-calibrated digital PLL in 90 nm CMOS process,” in Dig. Tech. Papers ISSCC'04, Feb. 2004, pp. 488–489.
- (2004) Dig. Tech. Papers ISSCC'04 , pp. 488-489
- Lin, J.¹ Haroun, B.² Foo, T.³ Wang, J.-S.⁴ Helmick, B.⁵ Randall, S.⁶ Mayhugh, T.⁷ Barr, C.⁸ Kirkpartick, J.⁹

3
- 11144297886
- A robust digital delay line architecture in a 0.13-μm CMOS technology node for reduced design and process sensitivities
- Mar.
- P. Raha, S. Randall, R. Jennings, B. Helmick, A. Amerasekera, and B. Haroun, “A robust digital delay line architecture in a 0.13-μm CMOS technology node for reduced design and process sensitivities,” in Proc. ISQED'02, Mar. 2002, pp. 148–153.
- (2002) Proc. ISQED'02 , pp. 148-153
- Raha, P.¹ Randall, S.² Jennings, R.³ Helmick, B.⁴ Amerasekera, A.⁵ Haroun, B.⁶

4
- 0142008437
- Portable digital clock generator for digital signal processing applications
- Sep.
- T. Olsson and P. Nilsson, “Portable digital clock generator for digital signal processing applications,” Electron. Lett., vol. 39, pp. 1372–1374, Sep. 2003.
- (2003) Electron. Lett. , vol.39 , pp. 1372-1374
- Olsson, T.¹ Nilsson, P.²

5
- 0037968905
- A delay-line based DCO for multimedia applications using digital standard cells only
- Feb.
- E. Roth, M. Thalmann, N. Felber, and W. Fichtner, “A delay-line based DCO for multimedia applications using digital standard cells only,” in Dig. Tech. Papers ISSCC'03, Feb. 2003, pp. 133-432.
- (2003) Dig. Tech. Papers ISSCC'03 , pp. 133-432
- Roth, E.¹ Thalmann, M.² Felber, N.³ Fichtner, W.⁴

6
- 0037319653
- An all digital phase-locked loop for high-speed clock generation
- Feb.
- C.-C. Chung and C.-Y. Lee, “An all digital phase-locked loop for high-speed clock generation,” IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 347–351, Feb. 2003.
- (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.2 , pp. 347-351
- Chung, C.-C.¹ Lee, C.-Y.²

7
- 0003850954
- Digital Integrated Circuits—A Design Perspectives
- Englewood Cliffs, NJ: Prentice-Hall
- J. M. Rabaey, Digital Integrated Circuits—A Design Perspectives. Englewood Cliffs, NJ: Prentice-Hall, 1996.
- (1996)
- Rabaey, J.M.¹

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