A 1.7mW all digital phase-locked loop with new gain generator and low power DCO

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 4867-4870

  Chao, Tzu Chiang ^a   Hwang, Wei ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATOR CIRCUITS; DIGITAL CIRCUITS; ELECTRIC POWER UTILIZATION; GAIN MEASUREMENT; NATURAL FREQUENCIES;

CLOCK CYCLES; FREQUENCY COMPARATORS; FREQUENCY LOCKING; FREQUENCY RANGE; PHASE DETECTORS;

PHASE LOCKED LOOPS;

EID: 34547334358     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. T. Olsson and, P. Nilsson, "A digital PLL made from standard cell," in Proc. 15th ECCTD, pp.277-280, 2001.
2. T. Olsson and P. Nilsson, "A digitally controlled PLL for SoC applications," IEEE J. Solid-State Circuits, Vol. 39, pp.751-760, May 2004.
3. J. Dunning, G. Garcia, J. Luhdherg, and E. Nuckolls, "An ALL Digital Phase-Locked Loop with 50-cycle Lock Time Suitable for High Performance Microprocessors," IEEE J. Solid-State Circuits, Vol.30, pp.412-422, Apr. 1995.