A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 6, 2006, Pages 1275-1285

  Chen, Pao Lung ^a,b,c   Chung, Ching Che ^a,b   Yang, Jyh Neng ^a,b   Lee, Chen Yi ^a,b  

^a IEEE   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c CHIN MIN INSTITUTE OF TECHNOLOGY   (Taiwan)

Author keywords

Clock generator; Digitally controlled oscillator (DCO); Digitally controlled varactor (DCV); Dynamic frequency counting (DFC); Phase locked loop (PLL)

Indexed keywords

CLOCK GENERATORS; DIGITALLY CONTROLLED OSCILLATOR (DCO); DIGITALLY CONTROLLED VARACTOR (DCV); DYNAMIC FREQUENCY COUNTING (DFC);

DIGITAL DEVICES; FREQUENCY SYNTHESIZERS; JITTER; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; VARACTORS;

ELECTRIC CLOCKS;

EID: 33746657329     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.874273     Document Type: Article

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