Design and analysis of a portable high-speed clock generator

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 48, Issue 4, 2001, Pages 367-375

  Hsu, T Y ^a   Wang, C C ^a   Lee, C Y ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

ADPLL; Clock generator; Frequency synthesizer; Full pull in range; HDL; Low jitter

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; FREQUENCY SYNTHESIZERS; INTEGRATED CIRCUIT TESTING; JITTER; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; TIMING CIRCUITS;

ALL-DIGITAL PHASE LOCKED LOOP; PEAK-TO-PEAK JITTER; PORTABLE CLOCK GENERATOR; PRUNE AND SEARCH ALGORITHM;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035300186     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.933795     Document Type: Article

References (8)

1. Fully-integrated CMOS phased-locked loop with 15 to 240 MHz locking range and ±50 ps jitter
2. Low-jitter and process-independent DLL and PLL based on self-biased techniques
3. A 360 MHz 3 V CMOS PLL with 1 V peak-to-peak power supply noise tolerance
4. A high-speed, low-power clock generator for a microprocessor
5. An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors
6. An all digital phase-locked loop (ADPLL) based clock recovery circuit