-
1
-
-
0031143856
-
A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL
-
May
-
S. Kim et al., "A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL," IEEE J. Solid-State Circuits, vol. 32, pp. 691-699, May 1997.
-
(1997)
IEEE J. Solid-state Circuits
, vol.32
, pp. 691-699
-
-
Kim, S.1
-
2
-
-
0030291248
-
A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for microprocessor clock generation
-
Nov.
-
V. Kaenel et al., "A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for microprocessor clock generation," IEEE J. Solid-State Circuits, vol. 31, pp. 1715-1722, Nov. 1996.
-
(1996)
IEEE J. Solid-state Circuits
, vol.31
, pp. 1715-1722
-
-
Kaenel, V.1
-
3
-
-
0030290680
-
Low-jitter process-independent DLL and PLL based on self-biased techniques
-
Nov.
-
J. Maneatic et al., "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.
-
(1996)
IEEE J. Solid-state Circuits
, vol.31
, pp. 1723-1732
-
-
Maneatic, J.1
-
4
-
-
0033681625
-
A lowjitter and low power phase-locked loop design
-
Geneva, Switzerland, May
-
K.-H. Chen, H.-S.Huan-Sen Liao, and L.-J.Lin-Jiunn Tzou, "A lowjitter and low power phase-locked loop design," in Proc. 2000 IEEE Int. Symp., vol. 2, Geneva, Switzerland, May 2000.
-
(2000)
Proc. 2000 IEEE Int. Symp.
, vol.2
-
-
Chen, K.-H.1
Uan-Sen Liao, H.-S.2
Lin-Jiunn Tzou, L.-J.3
-
5
-
-
0030105412
-
A study of phase noise in CMOS oscillators
-
Mar.
-
B. Razavi, "A study of phase noise in CMOS oscillators," IEEE J. Solid-State Circuits, vol. 31, pp. 331-343, Mar. 1996.
-
(1996)
IEEE J. Solid-state Circuits
, vol.31
, pp. 331-343
-
-
Razavi, B.1
-
6
-
-
0034829270
-
A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO
-
K. Minami and T.Takanori Sato et al., "A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO," in Proc. IEEE 2001 Custom Integrated Circuits Conf., pp. 213-216.
-
(2001)
Proc. IEEE 2001 Custom Integrated Circuits Conf.
, pp. 213-216
-
-
Minami, K.1
Takanori Sato, T.2
-
7
-
-
0034248698
-
A low-noise fast-lock phase-locked loop with bandwidth control
-
Aug.
-
J. Lee and B. Kim, "A low-noise fast-lock phase-locked loop with bandwidth control," IEEE J. Solid-State Circuits, vol. 35, pp. 1137-1145, Aug. 2000.
-
(2000)
IEEE J. Solid-state Circuits
, vol.35
, pp. 1137-1145
-
-
Lee, J.1
Kim, B.2
-
8
-
-
0034781618
-
A low-noise fast-settling PLL with extended loop bandwidth enhancement by new adaptation technique
-
Y. Tang, Y. Zhou, S. Bibykl, and M. Ismail, "A low-noise fast-settling PLL with extended loop bandwidth enhancement by new adaptation technique," in Proc. 14th Annu. IEEE Int. ASIC/SOC Conf., 2001, pp. 93-97.
-
(2001)
Proc. 14th Annu. IEEE Int. ASIC/SOC Conf.
, pp. 93-97
-
-
Tang, Y.1
Zhou, Y.2
Bibykl, S.3
Ismail, M.4
-
9
-
-
0034298112
-
Fast-switching frequency synthesizer with a discriminator-aided phase detector
-
Oct.
-
C.-Y. Yang and S.-I. Liu, "Fast-switching frequency synthesizer with a discriminator-aided phase detector," IEEE J. Solid-State Circuits, vol. 35, pp. 1445-1452, Oct. 2000.
-
(2000)
IEEE J. Solid-state Circuits
, vol.35
, pp. 1445-1452
-
-
Yang, C.-Y.1
Liu, S.-I.2
-
10
-
-
0036564108
-
Analysis and minimization of phase noise of the digital hybrid PLL frequency synthesizer
-
May
-
H. Ryu and H.-S. Lee, "Analysis and minimization of phase noise of the digital hybrid PLL frequency synthesizer," IEEE Trans. Consumer Electron., vol. 48, May 2002.
-
(2002)
IEEE Trans. Consumer Electron.
, vol.48
-
-
Ryu, H.1
Lee, H.-S.2
-
11
-
-
84948420984
-
Timing jitter measurement of 10 Gbps bit clock signals using frequency division
-
T. J. Yamaguchi et al., "Timing jitter measurement of 10 Gbps bit clock signals using frequency division," in Proc. 20th IEEE VLSI Test Symp., 2002, pp. 207-212.
-
(2002)
Proc. 20th IEEE VLSI Test Symp.
, pp. 207-212
-
-
Yamaguchi, T.J.1
|