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Volumn 50, Issue 11, 2003, Pages 892-896

A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop

Author keywords

Coarse tuning loop; Dual slope; Fast locking; Fine tuning loop; Phased locked loop (PLL)

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; FREQUENCIES; JITTER; MICROPROCESSOR CHIPS; PRODUCT DESIGN; TUNING;

EID: 0345293100     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSII.2003.819130     Document Type: Article
Times cited : (41)

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  • 8
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    • Y. Tang, Y. Zhou, S. Bibykl, and M. Ismail, "A low-noise fast-settling PLL with extended loop bandwidth enhancement by new adaptation technique," in Proc. 14th Annu. IEEE Int. ASIC/SOC Conf., 2001, pp. 93-97.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.