A low-jitter ADPLL via a suppressive digital filter and an interpolation-based locking scheme

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 1, 2011, Pages 165-170

  Hsu, Hsuan Jung ^a   Huang, Shi Yu ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

All digital phase locked loop (ADPLL); digital filter; digitally controlled oscillator (DCO); frequency interpolation; locking algorithm

Indexed keywords

ALL DIGITAL PHASE LOCKED LOOP; CLOCK-JITTER; DIGITALLY CONTROLLED OSCILLATORS; FREQUENCY INTERPOLATION; JITTER PERFORMANCE; JITTER RMS; LOCKING ALGORITHM; LOCKING SCHEMES; LOOP FILTER; MEASUREMENT RESULTS; PHASE ERROR; PHASE-LOCKING; SIMULATION RESULT;

ALGORITHMS; DIGITAL FILTERS; INTERPOLATION; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS;

JITTER;

EID: 78650909867     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2030410     Document Type: Article

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