An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 2, 2003, Pages 198-204

  Watanabe, Takamoto ^a   Yamauchi, Shigenori ^a  

^a DENSO CORPORATION   (Japan)

Author keywords

All digital; All digital phase locked loop (ADPLL); Clock generator; CMOS; Delay line; Digitally controlled oscillator (DCO); Frequency multiplication; Phase comparator; Phase locked loop (PLL); Synthesizer; Time to digital converter (TDC)

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC DELAY LINES; FREQUENCY MULTIPLYING CIRCUITS; JITTER; PHASE COMPARATORS;

DIGITALLY CONTROLLED OSCILLATORS (DCO);

PHASE LOCKED LOOPS;

EID: 0037319509     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.807405     Document Type: Article

References (11)

1. H. Ahn and D. J. Allstot, "A low-jitter 1.9-V CMOS PLL for Ultra-SPARC microprocessor applications," IEEE J. Solid-State Circuits, vol. 35, pp. 450-454, Mar. 2000.
2. Novof, J. Austin, R. Kelker, D. Strayer, and S. Wyatt, "Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 ps jitter," IEEE J. Solid-State Circuits, vol. 30, pp. 1259-1266, Nov. 1995.
3. W. Lindsey and C. Chie, "A survey of digital phase-locked loops," Proc. IEEE, vol. 69, pp. 410-430, Apr. 1981.
4. T. Hsu, B. Shieh, and C. Lee, "An all-digital phase-locked loop (ADPLL)-based clock recovery circuit," IEEE J. Solid-State Circuits, vol. 34, pp. 1063-1073, Aug. 1999.
5. J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, "An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors," IEEE J. Solid-State Circuits, vol. 30, pp. 412-422, Apr. 1995.
6. P. Nilsson and M. Torkelson, "A monolithic digital clock-generator for on-chip clocking of custom DSPs," IEEE J. Solid-State Circuits, vol. 31, pp. 700-706, May 1996.
7. B. Garlepp, K. Donnelly, J. Kim, P. Chan, J. Zerbe, C. Huang, C. Tran., C. Portmann, D. Stark, Y. Chan, T. Lee, and M. Horowitz, "A portable digital DLL for high-speed CMOS interface circuits," IEEE J. Solid-State Circuits, vol. 34, pp. 632-644, May 1999.
8. A. Hatakeyama, H. Mochizuki, T. Aikawa, M. Takita, Y. Ishii, H. Tsuboi, S. Fujioka, S. Yamaguchi, M. Koga, Y. Serizawa, K. Nishimura, K. Kawabata, Y. Okajima, M. Kawano, H. Kojima, K. Mizutani, T. Anezaki, M. Hasegawa, and M. Taguchi, "A 256-Mb SDRAM using a register-controlled digital DLL," IEEE J. Solid-State Circuits, vol. 32, pp. 1728-1733, Nov. 1997.
9. T. Watanabe, Y. Makino, Y. Ohtsuka, S. Akita, and T. Hattori, "A CMOS time-to-digital converter LSI with half-nanosecond resolution using a ring gate delay line," IEICE Trans. Electron., vol. E76-C, no. 12, pp. 1774-1779, Dec. 1993.
10. T. Watanabe, T. Mizuno, and Y. Makino, "A 14-bit 12 μV/LSB resolution A/D converter for sensors using only digital circuit with low-pass filter effect," in Proc. 8th IEEE ICECS, vol. II, 2001, pp. 677-680.
11. K. Kawamoto, S. Mizuno, H. Abe, Y. Higuchi, H. Ishihara, H. Fukumoto, T. Watanabe, S. Fujino, and I. Shirakawa, "A single-chip automotive control LSI using SOI BiCDMOS," Jpn. J. Appl. Phys., vol. 40, no. 4B, pp. 450-455, Apr. 2001.