Performance enhancement in multi gate tunneling field effect transistors by scaling the fin-width

Japanese Journal of Applied Physics

Volumn 49, Issue 4 PART 2, 2010, Pages

  Leonelli, Daniele ^a,b   Vandooren, Anne ^a   Rooyackers, Rita ^a   Verhulst, Anne S ^a,b   De Gendt, Stefan ^a,b   Heyns, Marc M ^a,b   Groeseneken, Guido ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; ELECTRICAL CHARACTERIZATION; FIN WIDTHS; GATE STACKS; HIGH-K DIELECTRIC; LINEAR DEPENDENCE; LOW BIAS; METAL GATE; MULTI-GATES; MULTIPLE GATES; OUTPUT CHARACTERISTICS; PERFORMANCE ENHANCEMENTS; SQUARE ROOTS; SUPPLY VOLTAGES; TEMPERATURE DEPENDENCE; TUNNELING CURRENT; TUNNELING DEVICE;

ANALOG CIRCUITS; ELECTRON TUNNELING; FINS (HEAT EXCHANGE); FORCED CONVECTION; METALLIC COMPOUNDS; MOS DEVICES; TUNNELING (EXCAVATION);

FIELD EFFECT TRANSISTORS;

EID: 77952726377     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.49.04DC10     Document Type: Article

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