Fabrication, optimization and application of complementary multiple-gate tunneling FETs

2008 2nd IEEE International Nanoelectronics Conference, INEC 2008

Volumn , Issue , 2008, Pages 579-584

  Fulde, M ^a   Heigl, A ^a   Weis, M ^a   Wirnshofer, M ^a   Arnim, K V ^b   Nirschl, Th ^b   Sterkel, M ^a   Knoblinger, G ^c   Hansch, W ^a   Wachutka, G ^a   Schmitt Landsiedel, D ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b INFINEON TECHNOLOGIES AG   (Germany)

^c INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON TUNNELING; ELECTRONICS ENGINEERING; MESFET DEVICES; NANOELECTRONICS; OPTICAL DESIGN; OPTIMIZATION; TUNNELING (EXCAVATION);

ANALOG DEVICES; CHANNEL LENGTHS; DEVICE SIMULATIONS; DEVICE STRUCTURES; DOPING PROFILES; GATE TUNNELLING; LOW-TEMPERATURE DEPENDENCE; MATCHING BEHAVIOR; MULTIPLE-GATE; ON-CURRENTS; POTENTIAL APPLICATIONS; TUNNELING CURRENTS; VOLTAGE REFERENCE;

EXCAVATION;

EID: 52649132943     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/INEC.2008.4585554     Document Type: Conference Paper

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