Demonstration of tunneling FETs based on highly scalable vertical silicon nanowires

IEEE Electron Device Letters

Volumn 30, Issue 7, 2009, Pages 754-756

  Chen, Z X ^a,b   Yu, H Y ^a,b   Singh, N ^b   Shen, N S ^b   Sayanthan, R D ^b   Lo, G Q ^b   Kwong, D L ^b  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

Gate all around (GAA); Top down; Tunneling field effect transistor (TFET); Vertical silicon nanowire (SiNW)

Indexed keywords

CMOS-COMPATIBLE TECHNOLOGY; GATE LENGTH; GATE-ALL-AROUND (GAA); HETEROSTRUCTURES; HIGH-DENSITY APPLICATIONS; SILICON NANOWIRES; SUBTHRESHOLD SWING; TOP-DOWN; TUNNELING FET; TUNNELING FIELD-EFFECT TRANSISTOR (TFET); TUNNELING FIELD-EFFECT TRANSISTORS; TUNNELING JUNCTIONS; ULTRA-LOW POWER; VERTICAL SILICON NANOWIRE (SINW);

ELECTRIC WIRE; FIELD EFFECT TRANSISTORS; GALLIUM ALLOYS; GATES (TRANSISTOR); NANOWIRES; WIND TUNNELS;

TUNNELING (EXCAVATION);

EID: 67650608173     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2021079     Document Type: Article

References (19)

1. C. Hu, "Green transistor as a solution to the IC power crisis," in Proc. 9th Int. Conf. Solid-State Integr. Circuit Technol., 2008, pp. 16-20.
2. W. M. Reddick and G. A. J. Amaratunga, "Silicon surface tunnel transistor," Appl. Phys. Lett., vol. 67, no. 4, pp. 494-496, Jul. 1995.
3. M. Born, K. K. Bhuwalka, M. Schindler, U. Abelein, M. Schmidt, T. Sulima, and I. Eisele, "Tunnel FET: A CMOS device for high temperature applications," in Proc. 25th Int. Conf. Microelectron., 2006, pp. 124-127.
4. W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, "Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec," IEEE Electron Device Lett., vol. 28, no. 8, pp. 743-745, Aug. 2007.
5. K. Boucart and A. M. Ionescu, "Double-gate tunnel FET with high-κ gate dielectric," IEEE Trans. Electron Devices, vol. 54, no. 7, pp. 1725-1733, Jul. 2007.
6. P.-F. Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M. Weis, D. Schmitt-Landsiedel, and W. Hansch, "Complementary tunneling transistor for low power application," Solid State Electron., vol. 48, no. 12, pp. 2281-2286, Dec. 2004.
7. N. B. Patel, A. Ramesha, and S. Mahapatra, "Performance enhancement of the tunnel field effect transistor using a SiGe source," in Proc. Int. Workshop Phys. Semicond. Devices, 2007, pp. 111-114.
8. K. K. Bhuwalka, J. Schulze, and I. Eisele, "Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering," IEEE Trans. Electron Devices, vol. 52, no. 5, pp. 909-917, May 2005.
9. T. Krishnamohan, D. Kim, S. Raghunathan, and K. C. Saraswat, "Double-gate strained-Ge heterostructure tunnelling FET (TFET) with record high drive current and < 60 mV/dec subthreshold slope," in IEDM Tech. Dig., 2008, pp. 947-949.
10. E.-H. Toh, G. H. Wang, L. Chan, G. Samudra, and Y.-C. Yeo, "Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction," Appl. Phys. Lett., vol. 91, no. 24, p. 243 505, Dec. 2007.
11. O. M. Nayfeh, C. N. Chleirigh, J. Hennessy, L. Gomez, J. L. Hoyt, and D. A. Antoniadis, "Design of tunneling field-effect transistors using strained-silicon/strained-germanium type-II staggered heterojunctions," IEEE Electron Device Lett., vol. 29, no. 9, pp. 1074-1077, Sep. 2008.
12. A. S. Verhulst, W. G. Vandenberghe, K. Maex, S. De Gendt, and M. M. Heyns, "Complementary silicon-based heterostructure tunnel-FETs with high tunnel rates," IEEE Electron Device Lett., vol. 29, no. 12, pp. 1398-1401, Dec. 2008.
13. P. F. Wang, T. Nirschl, D. Schmitt-Landsiedel, and W. Hansch, "Simulation of the Esaki-tunneling FET," Solid State Electron., vol. 47, no. 7, pp. 1187-1192, Jul. 2003.
14. J. Knoch and J. Appenzeller, "A novel concept for field-effect transistors - The tunneling carbon nanotube FET," in Proc. 63rd DRC 2005, pp. 153-156.
15. S. O. Koswatta, D. E. Nikonov, and M. S. Lundstrom, "Computational study of carbon nanotube p-i-n tunnel FETs," in IEDM Tech. Dig., 2005, pp. 518-521.
16. W. Y. Choi, J. D. Lee, and B.-G. Park, "Novel tunneling devices with multi-functionality," Jpn. J. Appl. Phys., vol. 46, no. 4B, pp. 2622-2625, 2007.
17. N. Singh, K. D. Buddharaju, S. K. Manhas, A. Agarwal, S. C. Rustagi, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, "Si, SiGe nanowire devices by top-down technology and their applications," IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3107-3118, Nov. 2008.
18. J. Goldberger, A. I. Hochbaum, R. Fan, and P. Yang, "Silicon vertically integrated nanowire field effect transistors," Nano Lett., vol. 6, no. 5, pp. 973-977, 2006.
19. B. Yang, K. D. Buddharaju, S. H. G. Teo, N. Singh, G. Q. Lo, and D.-L. Kwong, "Vertical silicon-nanowire formation and gate-all-around MOSFET," IEEE Electron Device Lett., vol. 29, no. 7, pp. 791-794, Jul. 2008.