An analytical placer for mixed-size 3D placement

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2010, Pages 61-66

  Cong, Jason ^a,b   Luo, Guojie ^a  

^a Engineering IV   (United States)

^b CALIFORNIA NANOSYSTEMS INSTITUTE   (United States)

Author keywords

3D integration; Analytical method; Placement

Indexed keywords

3-D INTEGRATION; ANALYTICAL METHOD; FLOORPLANS; FUNCTIONAL UNITS; INITIAL SOLUTION; INTELLECTUAL PROPERTY BLOCKS; MIXED-SIZE PLACEMENT; PLACEMENT METHODS; RUNTIMES; STANDARD CELL; STEPSIZE; THROUGH SILICON VIAS; WIRE LENGTH;

ELECTRIC BATTERIES;

THREE DIMENSIONAL;

EID: 77952275250     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1735023.1735044     Document Type: Conference Paper

References (20)

1. S.N. Adya and I.L. Markov, "Consistent Placement of Macro-Blocks Using Floorplanning and Standard-Cell Placement," Proceedings of the 2002 International Symposium on Physical Design, pp. 12-17, 2002.
2. S.N. Adya, S. Chaturvedi, J.A. Roy, D.A. Papa, and I.L. Markov, "Unification of Partitioning, Placement and Floorplanning," Proceedings of the 2004 IEEE/ACM International Conference on Computer-Aided Design, pp. 550-557, 2004.
3. C. Alpert, A. Kahng, G.-J. Nam, S. Reda, and P. Villarrubia, "A Semi-persistent Clustering Technique for VLSI Circuit Placement," Proceedings of the 2005 International Symposium on Physical Design, pp. 200-207, 2005. (Pubitemid 41816866)
4. K. Bernstein, P. Andry, J. Cann, P. Emma, D. Greenberg, W. Haensch, M. Ignatowski, S. Koester, J. Magerlein, R. Puri, and A. Young, "Interconnects in the Third Dimension: Design Challenges for 3D ICs," Proceedings of the 44th Annual Conference on Design Automation, pp. 562-567, 2007. (Pubitemid 47130028)
5. T.F. Chan, J. Cong, and K. Sze, "Multilevel Generalized Force-directed Method for Circuit Placement," Proceedings of the 2005 International Symposium on Physical Design, pp. 185-192, 2005. (Pubitemid 41816864)
6. T.F. Chan, J. Cong, J.R. Shinnerl, K. Sze, and M. Xie, "mPL6: Enhancement Multilevel Mixed-Size Placement with Congestion Control," in Modern Circuit Placement, ed. G.-J. Nam and J. Cong, Springer Publishers, 2007.
7. C. Chiang and S. Sinha, "The Road to 3D EDA Tool Readiness," Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, pp. 429-436, 2009.
8. J. Cong and G. Luo, "A Multilevel Analytical Placement for 3D ICs," Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, pp. 361-366, 2009.
9. J. Cong and M. Xie, "A Robust Mixed-Size Legalization and Detailed Placement Algorithm," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 8, pp. 1349-1362, August 2008.
10. J. Cong, G. Luo, J. Wei, and Y. Zhang, "Thermal-Aware 3D IC Placement Via Transformation," Proceedings of the 2007 Conference on Asia South Pacific Design Automation, pp. 780-785, 2007.
11. J. Cong, G. Luo, and E. Radke, "Highly Efficient Gradient Computation for Density-Constrained Analytical Placement," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, no. 12, pp. 2133-2144, 2008.
12. J. Cong, J. Wei, and Y. Zhang, "A Thermal-Driven Floorplanning Algorithm for 3D ICs," Proceedings of the 2004 IEEE/ACM International Conference on Computer-Aided Design, pp. 306-313, 2004.
13. W.R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A.M. Sule, M. Steer, and P.D. Franzon, "Demystifying 3D ICs: The Pros and Cons of Going Vertical," IEEE Design & Test of Computers, vol. 22, no. 6, pp. 498-510, 2005.
14. B. Goplen and S. Sapatnekar, "Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach," Proceedings of the 2003 IEEE/ACM International Conference on Computer-Aided Design, pp. 86, 2003.
15. B. Goplen and S. Spatnekar, "Placement of 3D ICs with Thermal and Interlayer Via Considerations," Proceedings of the 44th Annual Conference on Design Automation, pp. 626-631, 2007. (Pubitemid 47130040)
16. D. Hill, "Method and System for High Speed Detailed Placement of Cells within an Integrated Circuit Design," US Patent 6370673, April 9, 2002.
17. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, "Multilevel hypergraph partitioning: applications in VLSI domain," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 7, no. 1, pp. 69-79, 1999.
18. J. Nocedal and S.J. Wright, "Numerical Optimization 2nd ed.," Springer, 2006.
19. H. Yan, Q. Zhou, and X. Hong, "Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm," Proceedings of the 9th International Symposium on Quality Electronic Design, pp. 289-292, 2008.
20. http://vlsicad.eecs.umich.edu/BK/ICCAD04bench/