Multilevel hypergraph partitioning: Applications in VLSI domain

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 1, 1999, Pages 69-79

  Karypis, George ^b   Aggarwal, Rajat ^c   Kumar, Vipin ^a,b   Shekhar, Shashi ^a,b  

^a IEEE

^b University of Minnesota   (United States)

^c Lattice Semiconductor Corporation   (United States)

Author keywords

Circuit partitioning; Hypergraph partitioning; Multilevel algorithms

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT;

MULTILEVEL HYPERGRAPH PARTITIONING;

VLSI CIRCUITS;

EID: 0033099622     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.748202     Document Type: Article

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