Signature-based SER analysis and design of logic circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 1, 2009, Pages 74-86

  Krishnaswamy, Smita ^a   Plaza, Stephen M ^b   Markov, Igor L ^c   Hayes, John P ^c  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b SYNOPSYS INC   (United States)

^c UNIVERSITY OF MICHIGAN   (United States)

Author keywords

B.7.2.C Hardware; Fault tolerance; Logic design; Performance and reliability; Redundant design B.9.1 hardware; Reliability; Reliability and testing; Testing

Indexed keywords

B.7.2.C HARDWARE; HARDWARE FAULTS; HARDWARE RELIABILITY; PERFORMANCE AND RELIABILITY; REDUNDANT DESIGN;

COMPUTER AIDED DESIGN; ERROR ANALYSIS; FAULT TOLERANCE; INTEGRATED CIRCUIT MANUFACTURE; LOGIC DESIGN; OBSERVABILITY; QUALITY ASSURANCE; RELIABILITY ANALYSIS; SWITCHING CIRCUITS;

LOGIC CIRCUITS;

EID: 77950982557     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.2009139     Document Type: Article

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