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Volumn , Issue , 2006, Pages 502-509

Soft error reduction in combinational logic using gate resizing and flipflop selection

Author keywords

[No Author keywords available]

Indexed keywords

AREA OVERHEAD; CIRCUIT OPTIMIZATION; CO-OPTIMIZATION; COMBINATIONAL LOGICS; COMPUTER-AIDED DESIGN; EXPERIMENTAL RESULTS; GATE SIZING; INTERNATIONAL CONFERENCES; JOINT OPTIMIZATION; OPTIMIZATION ALGORITHMS; OPTIMIZATION APPROACH (OOA); RUN TIMES; SELECTION METHODS; SOFT ERROR RATES (SER); SOFT ERRORS; SOFT ERRORS (SE); TEMPORAL MASKING (TM); VLSI DESIGNS;

EID: 42649146134     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320165     Document Type: Conference Paper
Times cited : (66)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.