-
1
-
-
21244491597
-
Soft errors in advanced computer systems
-
May
-
R. Baumann, "Soft errors in advanced computer systems," IEEE Design and Test of Computers (D & T), 22 (3), pp. 258-266, May 2005.
-
(2005)
IEEE Design and Test of Computers (D & T)
, vol.22
, Issue.3
, pp. 258-266
-
-
Baumann, R.1
-
2
-
-
0036931372
-
Modeling the effect of technology trends on the soft error rate of combinational logic
-
Jun
-
P. Shivakumar, M. Kistler, S. Keckler, D. Burger, L. Alvisi, "Modeling the effect of technology trends on the soft error rate of combinational logic," Intl. Conf. on Dependable Systems and Networks (DSN), pp. 389-398, Jun 2002.
-
(2002)
Intl. Conf. on Dependable Systems and Networks (DSN)
, pp. 389-398
-
-
Shivakumar, P.1
Kistler, M.2
Keckler, S.3
Burger, D.4
Alvisi, L.5
-
3
-
-
0034785079
-
Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18μm
-
Jun
-
T. Karnik, B. Bloechel, K. Soumyanath, V. De, S. Borkar, "Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18μm," Symp. on VLSI Circuits, pp. 61-62, Jun 2001.
-
(2001)
Symp. on VLSI Circuits
, pp. 61-62
-
-
Karnik, T.1
Bloechel, B.2
Soumyanath, K.3
De, V.4
Borkar, S.5
-
4
-
-
15044363155
-
Robust system design with built-in soft-error resilience
-
Feb
-
S. Mitra, N. Seifert, M. Zhang, Q. Shi, K. Kim, "Robust system design with built-in soft-error resilience," IEEE Computer, 38(2), pp. 43-52, Feb 2005.
-
(2005)
IEEE Computer
, vol.38
, Issue.2
, pp. 43-52
-
-
Mitra, S.1
Seifert, N.2
Zhang, M.3
Shi, Q.4
Kim, K.5
-
5
-
-
0242659354
-
Selective node engineering for chip-level soft error rate improvement
-
Jun
-
T. Karnik, S. Vangal, S. Veeramachaneni, R Hazucha, V. Erraguntla, S. Borkar, "Selective node engineering for chip-level soft error rate improvement," Symp. on VLSI Circuits, pp. 204-205, Jun 2002.
-
(2002)
Symp. on VLSI Circuits
, pp. 204-205
-
-
Karnik, T.1
Vangal, S.2
Veeramachaneni, S.3
Hazucha, R.4
Erraguntla, V.5
Borkar, S.6
-
6
-
-
27944502944
-
Logic soft errors in sub-65nm technologies design and CAD challenges
-
Jun
-
S. Mitra, T. Karnik, N. Seifert, M. Zhang, "Logic soft errors in sub-65nm technologies design and CAD challenges," Design Automation Conf. (DAC), pp. 2-3, Jun 2005.
-
(2005)
Design Automation Conf. (DAC)
, pp. 2-3
-
-
Mitra, S.1
Karnik, T.2
Seifert, N.3
Zhang, M.4
-
7
-
-
46149111854
-
A CMOS design technique for SEU hardening
-
Dec
-
M. Baze, S. Buechner, D. Mcmurrow, "A CMOS design technique for SEU hardening," IEEE Trans. on Nuclear Science (TNS), 47(6), pp. 263-2608, Dec 2000.
-
(2000)
IEEE Trans. on Nuclear Science (TNS)
, vol.47
, Issue.6
, pp. 263-2608
-
-
Baze, M.1
Buechner, S.2
Mcmurrow, D.3
-
8
-
-
0142184763
-
Cost-effective approach for reducing the soft error failure rate in logic circuits
-
Sep
-
K. Moharam, N. Touba, "Cost-effective approach for reducing the soft error failure rate in logic circuits," Intl. Test Conf. (ITC), pp. 893-901, Sep 2003.
-
(2003)
Intl. Test Conf. (ITC)
, pp. 893-901
-
-
Moharam, K.1
Touba, N.2
-
9
-
-
33646909420
-
Soft-error tolerance analysis and optimization of nanometer circuits
-
Mar
-
Y. Dhillon, A. Diril, A. Chatterjee, "Soft-error tolerance analysis and optimization of nanometer circuits," Design Automation and Test in Europe (DATE), pp. 288-293, Mar 2005.
-
(2005)
Design Automation and Test in Europe (DATE)
, pp. 288-293
-
-
Dhillon, Y.1
Diril, A.2
Chatterjee, A.3
-
10
-
-
16244405890
-
Cost effective radiation hardening technique for combinational logic
-
Nov
-
Q. Zhou, K. Mohanram, "Cost effective radiation hardening technique for combinational logic," Intl. Conf. on Computer-Aided Design (ICCAD), pp. 100-106, Nov 2004.
-
(2004)
Intl. Conf. on Computer-Aided Design (ICCAD)
, pp. 100-106
-
-
Zhou, Q.1
Mohanram, K.2
-
11
-
-
33745500660
-
Load and logic co-optimization for design of soft-error resilient nanometer CMOS circuits
-
Jul
-
Y. Dhillon, A. Diril, A. Chatterjee, C. Metra, "Load and logic co-optimization for design of soft-error resilient nanometer CMOS circuits," Intl. Online Testing Symp. (IOLTS), pp. 35-40, Jul 2005.
-
(2005)
Intl. Online Testing Symp. (IOLTS)
, pp. 35-40
-
-
Dhillon, Y.1
Diril, A.2
Chatterjee, A.3
Metra, C.4
-
12
-
-
84886731240
-
Improving transient error tolerance using robustness compiler (ROCO)
-
Mar
-
C. Zhao, S. Dey, "Improving transient error tolerance using robustness compiler (ROCO)," Intl. Symp. on Quality Electronic Design (ISQED), pp. 133-138, Mar 2006.
-
(2006)
Intl. Symp. on Quality Electronic Design (ISQED)
, pp. 133-138
-
-
Zhao, C.1
Dey, S.2
-
13
-
-
33947358456
-
An energy-efficient circuit technique for single event transient noise-tolerance
-
Jun
-
M. Zhang, N. Shanbhag, "An energy-efficient circuit technique for single event transient noise-tolerance," Intl. Symp. on Circuits and Systems (ISCAS), pp. 636-639, Jun 2005.
-
(2005)
Intl. Symp. on Circuits and Systems (ISCAS)
, pp. 636-639
-
-
Zhang, M.1
Shanbhag, N.2
-
14
-
-
84949185312
-
Soft error rate mitigation techniques for modern microcircuits
-
Apr
-
D. Mavis, P. Eaton, "Soft error rate mitigation techniques for modern microcircuits," Intl. Reliability Physics Symp. (IRPS), pp. 216-225, Apr 2002.
-
(2002)
Intl. Reliability Physics Symp. (IRPS)
, pp. 216-225
-
-
Mavis, D.1
Eaton, P.2
-
17
-
-
84886742846
-
Logic SER reduction through flipflop redesign
-
Mar
-
V. Joshi, R. R. Rao, D. Blaauw, D. Sylvester, "Logic SER reduction through flipflop redesign," Intl. Symp. on Quality Electronic Design (ISQED), pp. 611-616, Mar 2006.
-
(2006)
Intl. Symp. on Quality Electronic Design (ISQED)
, pp. 611-616
-
-
Joshi, V.1
Rao, R.R.2
Blaauw, D.3
Sylvester, D.4
-
18
-
-
84886735426
-
Time redundancy based scan flip-flop reuse to reduce SER of combinational logic
-
Mar
-
P. Elakkumanan, K. Prasad, R. Sridhar, "Time redundancy based scan flip-flop reuse to reduce SER of combinational logic," Intl. Symp. on Quality Electronic Design (ISQED), pp. 617-622, Mar 2006.
-
(2006)
Intl. Symp. on Quality Electronic Design (ISQED)
, pp. 617-622
-
-
Elakkumanan, P.1
Prasad, K.2
Sridhar, R.3
-
20
-
-
4444372346
-
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits
-
Jun
-
C. Zhao, X. Bai, S. Dey, "A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits," Design Automation Conf. (DAC), pp. 894-899, Jun 2004.
-
(2004)
Design Automation Conf. (DAC)
, pp. 894-899
-
-
Zhao, C.1
Bai, X.2
Dey, S.3
-
22
-
-
33748538027
-
SEAT-LA: A soft error analysis tool for combinational logic
-
Jan
-
R Rajaraman, J. Kim, N. Vijaykrishnan, Y. Xie, M. Irwin, "SEAT-LA: A soft error analysis tool for combinational logic," Intl. Conf. on VLSI Design (VLSID), pp. 499-502, Jan 2006.
-
(2006)
Intl. Conf. on VLSI Design (VLSID)
, pp. 499-502
-
-
Rajaraman, R.1
Kim, J.2
Vijaykrishnan, N.3
Xie, Y.4
Irwin, M.5
-
23
-
-
34047185427
-
An efficient static algorithm for computing the soft error rates of combinational circuits
-
Mar
-
R. R. Rao, K. Chopra, D. Blaauw, D. Sylvester, "An efficient static algorithm for computing the soft error rates of combinational circuits," Design Automation and Test in Europe (DATE), pp. 164-169, Mar 2006.
-
(2006)
Design Automation and Test in Europe (DATE)
, pp. 164-169
-
-
Rao, R.R.1
Chopra, K.2
Blaauw, D.3
Sylvester, D.4
-
25
-
-
0029752087
-
Critical charge calculations for a bipolar SRAM array
-
L. Freeman, "Critical charge calculations for a bipolar SRAM array," IBM Journal of Research & Development, 40(1), 1996.
-
(1996)
IBM Journal of Research & Development
, vol.40
, Issue.1
-
-
Freeman, L.1
-
26
-
-
0034450511
-
Impact of CMOS technology scaling on atmospheric neutron soft error rate
-
Dec
-
P. Hazucha, C. Svensson, "Impact of CMOS technology scaling on atmospheric neutron soft error rate," IEEE Trans. on Nuclear Science (TNS), 47(6), pp. 2586-2594, Dec 2000.
-
(2000)
IEEE Trans. on Nuclear Science (TNS)
, vol.47
, Issue.6
, pp. 2586-2594
-
-
Hazucha, P.1
Svensson, C.2
-
27
-
-
0002609165
-
A neural netlist often combinational benchmark circuits and translator in Fortran
-
Jun
-
F. Brglez, H. Fujiwara, "A neural netlist often combinational benchmark circuits and translator in Fortran," Intl. Symp. on Circuits and Systems (ISCAS), pp. 663-698, Jun 1985.
-
(1985)
Intl. Symp. on Circuits and Systems (ISCAS)
, pp. 663-698
-
-
Brglez, F.1
Fujiwara, H.2
|