Circuit optimization by rewiring

IEEE Transactions on Computers

Volumn 48, Issue 9, 1999, Pages 962-970

  Chang, Shih Chieh ^a,b   Van Ginneken, Lukas P P P ^a,c   Marek Sadowska, Malgorzata ^a,d  

^a IEEE

^b NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

^c MAGMA DESIGN AUTOMATION   (United States)

^d University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; ELECTRIC WIRING; INDUSTRIAL APPLICATIONS; LOGIC DESIGN; LOGIC GATES; MATHEMATICAL TRANSFORMATIONS; OPTIMIZATION; PERFORMANCE; VECTORS;

AUTOMATIC TEST PATTERN GENERATION; BOOLEAN OPTIMIZATION; FORCED MANDATORY ASSIGNMENTS; LOGIC SYNTHESIS; OBSERVABILITY MANDATORY ASSIGNMENTS;

COMBINATORIAL CIRCUITS;

EID: 0033355046     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.795224     Document Type: Article

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