Timing optimization by an improved redundancy addition and removal technique

European Design Automation Conference - Proceedings

Volumn , Issue , 1996, Pages 342-347

  Entrena, Luis A ^a   Espejo, Jose A ^a   Olias, Emilio ^a   Uceda, Javier ^a  

^a UNIVERSIDAD CARLOS III DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; CRITICAL PATH ANALYSIS; LOGIC CIRCUITS; LOGIC DESIGN; LOGIC GATES; MATHEMATICAL TRANSFORMATIONS; OPTIMIZATION; REDUNDANCY; SEQUENTIAL CIRCUITS;

AUTOMATIC TEST PATTERN GENERATION; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC NETWORK; LOGIC OPTIMIZATION TRANSFORMS; REDUNDANCY ADDITION AND REMOVAL; TIMING OPTIMIZATION;

TIMING CIRCUITS;

EID: 0029764729     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)