A 5865 GHz neutralized CMOS power amplifier with PAE above 10% at 1-V supply

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 3, 2010, Pages 554-564

  Chan, Wei L ^a   Long, John R ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Balun; Broadband; CMOS; Differential shielding; Low supply voltage; Millimeter wave; Neutralization; Power amplifier; Transformer coupling

Indexed keywords

BULK CMOS; CMOS; CMOS POWER AMPLIFIERS; DIFFERENTIAL SHIELDING; GAIN STAGES; GATE DRAIN; GHZ BAND; INPUT AND OUTPUTS; LOW SUPPLY VOLTAGES; ON CHIPS; POWER GAINS; PSEUDO DIFFERENTIAL; REVERSE ISOLATION; SATURATED OUTPUT POWER; SMALL-SIGNAL GAIN;

CMOS INTEGRATED CIRCUITS; HETEROJUNCTION BIPOLAR TRANSISTORS; MILLIMETER WAVE DEVICES; MILLIMETER WAVES; POWER AMPLIFIERS; SHIELDING;

BROADBAND AMPLIFIERS;

EID: 77649151751     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2039274     Document Type: Article

References (34)

1. C. Marco, D. Chowdhury, C. Thakkar, L.-K. Kong, M. Tabesh, J.-D. Park, Y. Wang, B. Afshar, A. Gupta, A. Arbabian, S. Gambini, R. Zamani, A. M. Niknejad, and E. Alon, "A 90 nm CMOS low-power 60 GHz transceiver with integrated baseband circuitry," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2009, pp. 314-315.
2. J. Lee, Y. Huang, Y. Chen, H. Lu, and C. Chang, "A low-power fully integrated 60 GHz transceiver system with OOK modulation and on-board antenna assembly," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2009, pp. 316-317.
3. J. Borremans, K. Raczkowski, and P. Wambacq, "A digitally controlled compact 57-to-66 GHz front-end in 45 nm digital CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2009, pp. 492-493.
4. TG3c, IEEE Std 802.15.3c. [Online]. Available: http://www.ieee802.org/15/ pub/TG3c.html
5. "Ecma TC48 Draft Standard for High Rate 60 GHz WPANs," ECMA Int. [Online]. Available: http://www.ecma-international.org/activities/ Communications/tc48-2008-024-Rev3.doc
6. WirelessHD™ Specification Version 1.0 Overview, WirelessHD [Online]. Available: http://www.wirelesshd.org/pdfs/Wire-lessHD-Full-Overview- 071009.pdf
7. Y. Kawano, T. Suzuki, M. Sato, T. Hirose, and K. Joshin, "A 77 GHz transceiver in 90 nm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2009, pp. 310-311.
8. E. Laskin, M. Khanpour, R. Aroca, K. W. Tang, P. Garcia, and S. P. Voinigescu, "A 95 GHz receiver with fundamental-frequency VCO and static frequency divider in 65 nm digital CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2008, pp. 180-181.
9. S. Sankaran, C. Mao, E. Seok, D. Shim, C. Cao, R. Han, D. J. Arenas, D. B. Tanner, S. Hill, C.-M. Hung, and K. K. O., "Towards terahertz operation of CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2009, pp. 202-203.
10. H. Li, B. Jagannathan, J. Wang, T.-C. Su, S. Sweeney, J. J. Pekarik, and Y. Shi, "Technology scaling and device design for 350 GHz RF performance in a 45 nm bulk CMOS process," in Symp. VLSI Technology Dig. Tech. Papers, 2007, pp. 56-57.
11. W. L. Chan, J. R. Long, M. Spirito, and J. J. Pekarik, "A 60 GHz-band 1 V 11.5 dBm power amplifier with 11% PAE in 65 nm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2009, pp. 380-381.
12. D. Chowdhury, P. Reynaert, and A. M. Niknejad, "A 6 GHz 1 V +12.3 dBm transformer-coupled wideband PA in 90 nm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2008, pp. 560-561.
13. T. LaRocca and M.-C. F. Chang, "60 GHz CMOS differential and transformer-coupled power amplifier for compact design," in Proc. IEEE Radio Frequency Integrated Circuits Symp., 2008, pp. 65-68.
14. T. Yao, M. Q. Gordon, K. K. W. Tang, K. H. K. Yau, M.-T. Yang, P. Schvan, and S. P. Voinigescu, "Algorithmic design of CMOS LNAs and PAs for 60-GHz radio," IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1044-1057, May 2007.
15. M. Tanomura, Y. Hamada, S. Kishimoto, M. Ito, N. Orihashi, K. Maruhashi, and H. Shimawaki, "TX and RX front-ends for 60 GHz band in 90 nm standard bulk CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2008, pp. 558-559.
16. A. B. Grebene, Bipolar and MOS Analog Integrated Circuit Design. New York: Wiley, 1984, Chapter 8.
17. Z. Luo, A. Steegen, M. Eller, R. Mann, C. Baiocco, P. Nguyen, L. Kim, M. Hoinkis, V. Ku, V. Klee, F. Jamin, P. Wrschka, P. Shafer, W. Lin, S. Fang, A. Ajmera, W. Tan, D. Park, R. Mo, J. Lian, D. Vietzke, C. Coppock, A. Vayshenker, T. Hook, V. Chan, K. Kim, A. Cowley, S. Kim, E. Kaltalioglu, B. Zhang, S. Marokkey, Y. Lin, K. Lee, H. Zhu, M. Weybright, R. Rengarajan, J. Ku, T. Schiml, J. Sudijono, I. Yang, and C. Wann, "High performance and low power transistors integrated in 65 nm bulk CMOS technology," in Int. Electron Devices Meeting (IEDM) Dig. Tech. Papers, 2004, pp. 661-664.
18. Y. Jin, M. A. T. Sanduleanu, and J. R. Long, "A wideband millimeter-wave power amplifier with 20 dB linear power gain and +8 dBm maximum saturated output power," IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1553-1562, Jul. 2008.
19. T. S. D. Cheung and J. R. Long, "A 21-26-GHz SiGe bipolar power amplifier MMIC," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2583-2597, Dec. 2005.
20. J. Kang, K. Lee, J. Yoon, Y. Chung, S. Hwang, and B. Kim, "Differential CMOS linear power amplifier with 2nd harmonic termination at the common source node," in Proc. IEEE Radio Frequency Integrated Circuits Symp., 2005, pp. 443-446.
21. T. S. D. Cheung and J. R. Long, "Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits," IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1183-1200, May 2006.
22. U. R. Pfeiffer and D. Goren, "A 20 dBm fully-integrated 60 GHz SiGe power amplifier with automatic level control," IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1455-1463, Jul. 2007.
23. A. Siligaris, Y. Hamada, C. Mounet, C. Raynaud, B. Martineau, N. Deparis, N. Rolland, M. Fukaishi, and P. Vincent, "A 60 GHz power amplifier with 14.5 dBm saturation power and 25% peak PAE in CMOS 65 nm SOI," in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), 2009, pp. 168-171.
24. K. Raczkowski, S. Thijs, W. D. Raedt, B. Nauwelaers, and P. Wambacq, "50-to-67 GHz ESD-protected power amplifiers in digital 45 nm LP CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2009, pp. 382-383.
25. T. Suzuki, Y. Kawano, M. Sato, T. Hirose, and K. Joshin, "60 and 77 GHz power amplifiers in standard 90 nm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2008, pp. 562-563.
26. M. Varonen, M. Kärkkäinen, M. Kantanen, and K. A. I. Halonen, "Millimeter-wave integrated circuits in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 1991-2002, Sep. 2008.
27. S. Pinel, S. Sarkar, P. Sen, B. Perumana, D. Yeh, D. Dawn, and J. Laskar, "A 90 nm CMOS 60 GHz radio," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2008, pp. 130-131.
28. M. Khanpour, S. P. Voinigescu, and M. T. Yang, "A high-gain, low-noise, +6 dBm PA in 90 nm CMOS for 60-GHz radio," in Proc. IEEE Compound Semiconductor Integrated Circuits Symp., 2007, pp. 1-4.
29. C. Yu and J. S. Yuan, "MOS RF reliability subject to dynamic voltage stress - Modeling and analysis," IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1751-1758, Aug. 2005.
30. J. S. Yuan and J. Ma, "Evaluation of RF-stress effect on class-E MOS power amplifier efficiency," IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 430-434, Jan. 2008.
31. W.-C. Lin, T.-C. Wu, Y.-H. Tsai, L.-J. Du, and Y.-C. King, "Reliability evaluation of class-E and class-A power amplifiers with nanoscaled CMOS technology," IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1478-1483, Jul. 2005.
32. E. Li, E. Rosenbaum, L. F. Register, J. Tao, and P. Fang, "Hot carrier induced degradation in deep submicron MOSFETs at 100° C," in Proc. IEEE Int. Reliability Physics Symp. (IRPS), 2000, pp. 103-107.
33. L. Larcher, D. Sanzogni, R. Brama, A. Mazzanti, and F. Svelto, "Oxide breakdown after RF stress: Experimental analysis and effects on power amplifier operation," in Proc. IEEE Int. Reliability Physics Symp. (IRPS), 2006, pp. 283-288.
34. L. L. Lewyn, T. Ytterdal, C. Wulff, and K. Martin, "Analog circuit design in nanoscale CMOS techologies," Proc. IEEE, vol. 97, no. 10, pp. 1687-1714, Oct. 2009.