Technology scaling and device design for 350 GHz RF performance in a 45nm bulk CMOS process

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 56-57

  Li, Hongmei ^a   Jagannathan, Basanth ^b   Wang, Jing ^b   Su, Tai Chi ^b   Sweeney, Susan ^a   Pekarik, John J ^a   Shi, Yun ^a   Greenberg, David ^b   Jin, Zhenrong ^a   Groves, Robert ^b   Wagner, Lawrence ^b   Csutak, Sebastian ^a  

^a IBM   (United States)

^b Baker Hughes INTEQ ^*

Author keywords

[No Author keywords available]

Indexed keywords

BULK CMOS; DEVICE DESIGNS; POWER GAINS; RF PERFORMANCE; TECHNOLOGY SCALING; VLSI TECHNOLOGIES;

PROCESS ENGINEERING;

TECHNOLOGY;

EID: 47249141629     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339725     Document Type: Conference Paper

References (5)

1. D. V. Singh, et al., IEEE Elec. Dev. Letters, v.27, n.3, p. 191, Mar. 2006.
2. J. Yuan, et al., Symposium on VLSI Technology, p.100, 2006.
3. J. Wang, et al., submitted to RFIC 2007.
4. L.Tiemeijer, et al., IEEE Trans. Microw. Th. Tech., v.53, n.2, p.723, 2005.
5. S. Lee, et al., IEDM Tech. Dig., p.251, 2005.