Analog circuit design in nanoscale CMOS technologies

Proceedings of the IEEE

Volumn 97, Issue 10, 2009, Pages 1687-1714

  Lewyn, Lanny L ^a   Ytterdal, Trond ^b   Wulff, Carsten ^b   Martin, Kenneth ^c  

^a Lewyn Consulting Inc   (United States)

^b NORWEGIAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Norway)

^c Granite SemiCom   (Canada)

Author keywords

ADC survey; Analog; Analog to digital converters; CHE; CHISEL; CMOS; Design for manufacturing; Design for reliability; Device matching; Device scaling; DFM; DFR; Dielectric breakdown; Electromigration (EM); Excess overdrive (EOD); Figure of merit; GNR; HCI; WPE

Indexed keywords

ANALOG CIRCUITS; ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED SOFTWARE ENGINEERING; DIELECTRIC MATERIALS; ELECTRIC BREAKDOWN; ELECTRIC CURRENTS; ELECTROMIGRATION; ELECTRONIC DESIGN AUTOMATION; ENERGY EFFICIENCY; HOT CARRIERS; HUMAN COMPUTER INTERACTION; INTEGRATED CIRCUIT MANUFACTURE; NANORIBBONS; RELIABILITY; SURVEYS; TIMING CIRCUITS;

ANALOG; ANALOG TO DIGITAL CONVERTERS; CHISEL; DESIGN FOR MANUFACTURING; DESIGN FOR RELIABILITY; DEVICE MATCHING; DEVICE-SCALING; EXCESS OVERDRIVE (EOD); FIGURE OF MERITS;

INTEGRATED CIRCUIT DESIGN;

EID: 70349671329     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2009.2024663     Document Type: Article

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