Numerical strategies towards peta-scale simulations of nanoelectronics devices

Parallel Computing

Volumn 36, Issue 2-3, 2010, Pages 117-128

  Luisier, Mathieu ^a   Klimeck, Gerhard ^a  

^a Purdue University   (United States)

Author keywords

Atomistic device simulations; High performance computing; Nanoelectronics; Peta scale

Indexed keywords

ATOMISTIC DEVICES; DYNAMIC CORES; EXPERIMENTAL DATA; EXTENDED STRUCTURES; HIGH ELECTRON MOBILITY; HIGH PERFORMANCE COMPUTING; NANO TRANSISTORS; NANOWIRE TRANSISTORS; NUMERICAL STRATEGIES; OPEN BOUNDARY CONDITION; PARALLELIZATIONS; PEAK PERFORMANCE; PREDICTIVE SIMULATIONS; QUANTUM TRANSPORT; SIMULATION DOMAIN; SUSTAINED PERFORMANCE; WORK LOADS;

ELECTRON MOBILITY; NANOELECTRONICS; QUANTUM CHEMISTRY; QUANTUM ELECTRONICS; THREE DIMENSIONAL;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 77549087334     PISSN: 01678191     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.parco.2010.01.003     Document Type: Article

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