Test architecture design and optimization for three-dimensional SoCs

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 220-225

  Li, Jiang ^a,b   Lin, Huang ^a   Qiang, Xu ^a,b  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^b SHENZHEN INSTITUTES OF ADVANCED TECHNOLOGY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUIT; DIE BONDING; INTEGRATION CAPABILITY; MANUFACTURING COST; SCALE INTEGRATED CIRCUITS; SYSTEM ON CHIPS; TEST ACCESS MECHANISM; TEST ARCHITECTURE; TEST SOLUTIONS; TESTING TIME; THREE-DIMENSIONAL (3D);

DESIGN; DIES; INTEGRATED CIRCUITS; TESTING; THREE DIMENSIONAL; WAFER BONDING;

SIMULATED ANNEALING;

EID: 70350064467     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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