CASCADE: A standard supercell design methodology with congestion-driven placement for three-dimensional interconnect-heavy very large-scale integrated circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 7, 2007, Pages 1270-1282

  Zhou, Lili ^a,b   Wakayama, Cherry ^a,b   Shi, C J Richard ^a,b  

^a IEEE   (United States)

^b University of Washington   (United States)

Author keywords

3 D via assignment; Congestion driven placement; Interconnect heavy integrated circuits; Low density parity check (LDPC) decoder; Three dimensional integrated circuits (3 D ICs)

Indexed keywords

LOW DENSITY PARITY CHECK (LDPC) DECODER; PROBABILISTIC CONGESTION MODELS; ROUTING DENSITY; THREE DIMENSIONAL INTEGRATED CIRCUITS (3DIC);

DECODING; ELECTRIC NETWORK ANALYSIS; ELECTRIC WIRE; INTERCONNECTION NETWORKS; LOGIC GATES; SILICON ON INSULATOR TECHNOLOGY;

VLSI CIRCUITS;

EID: 34250769511     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.888266     Document Type: Article

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