-
1
-
-
0032164772
-
Wave-pipelining: A tutorial and research survey
-
Burleson W.P., Ciesielski M. Wave-pipelining: A tutorial and research survey. IEEE Trans. VLSI Syst. 6:(3):1998;464-474.
-
(1998)
IEEE Trans. VLSI Syst.
, vol.6
, Issue.3
, pp. 464-474
-
-
Burleson, W.P.1
Ciesielski, M.2
-
3
-
-
0026257568
-
A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture
-
Chappell T.I., Chappell B.A. A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture. IEEE J. Solid-State Circuits. 26:(11):1991;1577-1585.
-
(1991)
IEEE J. Solid-State Circuits
, vol.26
, Issue.11
, pp. 1577-1585
-
-
Chappell, T.I.1
Chappell, B.A.2
-
5
-
-
0015605213
-
Anomalous behaviour of synchronizer and arbiter circuits
-
Chaney T.J., Molnar C.E. Anomalous behaviour of synchronizer and arbiter circuits. IEEE Trans. Comput. C-22(4):1973;421-422.
-
(1973)
IEEE Trans. Comput.
, vol.C-22
, Issue.4
, pp. 421-422
-
-
Chaney, T.J.1
Molnar, C.E.2
-
6
-
-
0003705271
-
An introduction to asynchronous circuit design
-
Computer Science Department, University of Utah, September
-
A. Davis, S.M. Nowick. An introduction to asynchronous circuit design. Technical Report UUCS-97-013, Computer Science Department, University of Utah, September 1997.
-
(1997)
Technical Report
, vol.UUCS-97-013
-
-
Davis, A.1
Nowick, S.M.2
-
9
-
-
0029191713
-
Asynchronous design methodologies: An overview
-
Hauck S. Asynchronous design methodologies: An overview. In Proceedings of the IEEE. 83:(1):1995;69-93.
-
(1995)
Proceedings of the IEEE
, vol.83
, Issue.1
, pp. 69-93
-
-
Hauck, S.1
-
10
-
-
0031678886
-
Stefanos sidiropoulos. High-speed electrical signaling: Overview and limitations
-
Horowitz M., Yang C.-K.K. Stefanos Sidiropoulos. High-speed electrical signaling: Overview and limitations. IEEE Micro. 18:(1):1998;12-24.
-
(1998)
IEEE Micro
, vol.18
, Issue.1
, pp. 12-24
-
-
Horowitz, M.1
Yang, C.-K.K.2
-
12
-
-
0042774164
-
A program transformation approach to asynchronous vlsi design
-
M. Broy (Ed.), NATO ASI, Berlin: Springer
-
Martin A.J. A program transformation approach to asynchronous vlsi design. Broy M. Deductive Program Design, NATO ASI. 1996;Springer, Berlin.
-
(1996)
Deductive Program Design
-
-
Martin, A.J.1
-
17
-
-
0027677633
-
Delay-insensitive multi-ring structures
-
Sparsø J., Staunstrup J. Delay-insensitive multi-ring structures. INTEGRATION. 15:(3):1993;313-340.
-
(1993)
INTEGRATION
, vol.15
, Issue.3
, pp. 313-340
-
-
Sparsø, J.1
Staunstrup, J.2
-
18
-
-
0003510274
-
-
Los Altos, CA: Morgan Kaufmann Publishers, Inc
-
Sutherland I., Sproull B., Harris D. Logical Effort: Designing Fast CMOS Circuits. 1999;Morgan Kaufmann Publishers, Inc, Los Altos, CA.
-
(1999)
Logical Effort: Designing Fast CMOS Circuits
-
-
Sutherland, I.1
Sproull, B.2
Harris, D.3
-
23
-
-
0026259615
-
A zero-overhead self-timed 160ns 54b CMOS divider
-
Williams T.E., Horowitz M.A. A zero-overhead self-timed 160ns 54b CMOS divider. IEEE J. Solid-State Circuits. 26:(11):1991;1651-1661.
-
(1991)
IEEE J. Solid-State Circuits
, vol.26
, Issue.11
, pp. 1651-1661
-
-
Williams, T.E.1
Horowitz, M.A.2
|