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Volumn 27, Issue 9, 2003, Pages 409-419

Surfing: A robust form of wave pipelining using self-timed circuit techniques

Author keywords

Asynchronous circuits; Domino logic; Dynamical systems; Timing; Wave pipelining

Indexed keywords

DATA COMMUNICATION SYSTEMS; LOGIC GATES; TIMING CIRCUITS;

EID: 0041325254     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0141-9331(03)00091-7     Document Type: Conference Paper
Times cited : (10)

References (23)
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    • Burleson, W.P.1    Ciesielski, M.2
  • 3
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    • A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture
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    • Chaney, T.J.1    Molnar, C.E.2
  • 6
    • 0003705271 scopus 로고    scopus 로고
    • An introduction to asynchronous circuit design
    • Computer Science Department, University of Utah, September
    • A. Davis, S.M. Nowick. An introduction to asynchronous circuit design. Technical Report UUCS-97-013, Computer Science Department, University of Utah, September 1997.
    • (1997) Technical Report , vol.UUCS-97-013
    • Davis, A.1    Nowick, S.M.2
  • 9
    • 0029191713 scopus 로고
    • Asynchronous design methodologies: An overview
    • Hauck S. Asynchronous design methodologies: An overview. In Proceedings of the IEEE. 83:(1):1995;69-93.
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    • Hauck, S.1
  • 10
    • 0031678886 scopus 로고    scopus 로고
    • Stefanos sidiropoulos. High-speed electrical signaling: Overview and limitations
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    • Horowitz, M.1    Yang, C.-K.K.2
  • 12
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    • A program transformation approach to asynchronous vlsi design
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    • Delay-insensitive multi-ring structures
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    • A zero-overhead self-timed 160ns 54b CMOS divider
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.