On-chip variability sensor using phase-locked loop for detecting and correcting parametric timing failures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 2, 2010, Pages 270-280

  Kang, Kunhyuk ^a   Park, Sang Phill ^b   Kim, Keejong ^c   Roy, Kaushik ^b  

^a INTEL CORPORATION   (United States)

^b PURDUE UNIVERSITY   (United States)

^c BROADCOM CORPORATION   (United States)

Author keywords

Adaptive body biasing; Negative bias temperature instability (NBTI); Phase locked loop (PLL); Reliability; Sensor circuit; Variation resilience

Indexed keywords

ADAPTIVE BODY BIASING; BODY BIAS; CIRCUIT BLOCKS; CMOS TECHNOLOGY; CONTROL VOLTAGES; CONVENTIONAL APPROACH; CRITICAL APPLICATIONS; DEEP SUBMICROMETER TECHNOLOGIES; DESIGN REQUIREMENTS; DYNAMIC PERFORMANCE; FUTURE TECHNOLOGIES; MEASUREMENT RESULTS; NEGATIVE BIAS TEMPERATURE INSTABILITY; ON CHIPS; OPTIMIZATION ANALYSIS; PARAMETRIC YIELD; PERFORMANCE VARIABILITY; PHASE-LOCKED LOOP (PLL); PRODUCT RELIABILITY; REDUCTION IN AREA; RESILIENT SYSTEMS; SENSOR CIRCUIT; SUPPLY VOLTAGES; TEMPERATURE VARIATION; TEMPORAL RELIABILITY; TEST CHIPS; TIMING CONSTRAINTS; VOLTAGE CONTROLLED OSCILLATOR;

CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRONIC CIRCUIT TRACKING; NEGATIVE TEMPERATURE COEFFICIENT; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; QUALITY ASSURANCE; RELIABILITY; SIGNAL DETECTION; SPURIOUS SIGNAL NOISE; TEMPERATURE DISTRIBUTION; THERMODYNAMIC STABILITY; TIME MEASUREMENT; TIMING CIRCUITS;

SENSORS;

EID: 75549086869     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2010399     Document Type: Article

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