A fully integrated 0.13μm CMOS 10Gb ethernet transceiver with XAUI interface

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Lee, Hyung Rok ^a   Hwang, Moon Sang ^a   Lee, Bong Joon ^a   Kim, Young Deok ^a   Oh, Dohwan ^a   Kim, Jaeha ^a   Lee, Sang Hyun ^b   Jeong, Deog Kyoon ^a   Kim, Wonchan ^a  

^a Seoul National University   (South Korea)

^b Silicon Image Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ETHERNET TRANSCEIVERS; NOISE SENSITIVITY;

ALGORITHMS; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; INTERFACES (COMPUTER); NATURAL FREQUENCIES; TRANSCEIVERS; TUNING;

MICROPROCESSOR CHIPS;

EID: 2442668896     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. T. H. Lin et al., "A 900MHz 2.5mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop," J. Solid-State Circuits, vol. 36, pp. 424-431, Mar. 2001.
2. B. J. Lee et al., "A 2.5-10Gb/s CMOS Transceiver with Alternating Edge Sampling Phase Detection for Loop Characteristic Stabilization," ISSCC Dig. Tech. Papers, pp. 76-77, Feb. 2003.
3. K. Lee et al., "A CMOS Serial Link for Fully Duplexed Data Communication," IEEE J. Solid-State Circuits, vol. 30, pp. 353-364, Apr. 1995.
4. S.J Song et al., "A 4-Gb/s CMOS Clock and Data Recovery Circuit Using 1/8-Rate Clock Technique," IEEE J. Solid-State Circuits, vol. 38, pp. 1213-1219, Jul. 2003.
5. J. Cao et al., "OC-192 Transmitter and Receiver in Standard 0.18μm CMOS," IEEE J. Solid-State Circuits, vol. 37, pp. 1768-1780, Dec. 2002.