A vertical 4-bit SONOS flash memory and a unique 3-D vertical nor array structure

IEEE Transactions on Nanotechnology

Volumn 9, Issue 1, 2010, Pages 70-77

  Kim, Yoon ^a   Park, Il Han ^a   Cho, Seongjae ^a   Yun, Jang Gn ^a   Lee, Jung Hoon ^a   Kim, Doo Hyun ^a   Lee, Gil Sung ^a   Park, Se Hwan ^a   Lee, Dong Hua ^a   Sim, Won Bo ^a   Kim, Wandong ^a   Shin, Hyungcheol ^a   Lee, Jong Duk ^a   Park, Byung Gook ^a  

^a Seoul National University   (South Korea)

Author keywords

3 D array; Flash memory; Silicon oxide nitride oxide silicon (SONOS); Vertical channel

Indexed keywords

3-D ARRAY; 3D ARRAYS; ARRAY ARCHITECTURE; ARRAY STRUCTURES; FABRICATION METHOD; HIGH-DENSITY; MULTI-BITS; NOR FLASH MEMORY; NUMERICAL SIMULATION; OPERATION VOLTAGE; PROGRAM AND ERASE CHARACTERISTICS; SECOND-BIT EFFECT; SHORT-CHANNEL EFFECT; SILICON OXIDE NITRIDE OXIDE SILICONS; SMALLEST UNIT; SONOS FLASH MEMORY; VERTICAL CHANNELS;

MIXED CONVECTION; NITRIDES; SILICON OXIDES; THREE DIMENSIONAL;

FLASH MEMORY;

EID: 75449112614     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2009.2026173     Document Type: Article

References (18)

1. K. Kim and G. Jeong, "Memory technologies in the nano-era: Challenges and opportunities," in Proc. ISSCC, 2005, pp. 576-577.
2. C.-Y. Lu, T.-C. Lu, and R. Liu, "Non-volatile memory technology-Today and tomorrow," in Proc. 13th IPFA, 2006, pp. 18-23.
3. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and David, "NROM: Anovel localized trapping, 2-bit nonvolatile memory cell," IEEE Electron Device Lett., vol.21, no.6, pp. 543-545, Jun. 2000.
4. C.-H. Lee, C. Kang, J. Sim, J.-S. Lee, J. Kim, Y. Shin, K.-T. Park, S. Jeon, J. Sel,Y. Jeong, B. Choi,V.Kim,W. Jung, C.-I. Hyun, J. Choi, and K. Kim, "Charge trapping memory cell of TANOS (Si-oxide-SiN-Al2O3-TaN) structure compatible to conventional NAND flash memory," in Proc. Non-Volatile Semicond. Memory Workshop (NVSMW), 2006, pp. 54-55. (Pubitemid 44753351)
5. B. Y. Choi, B.-G. Park, Y. K. Lee, S. K. Sung, T. Y. Kim, E. S. Cho, H. J.Cho,C.W.Oh, S.H.Kim,D.W.Kim, C.-H.Lee, andD. Park, "Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50 nm NVM technology using outer sidewall spacer scheme with damascene gate process," in VLSI Tech. Dig., 2005, pp. 118-119.
6. J. H. Lee, "Two-bit/cell NFGM devices for high-density NOR flash memory," J. Semicond. Technol. Sci., vol.8, no.1, pp. 11-20, 2008.
7. C. W. Oh, S. H. Kim, N. Y. Kim, Y. L. Choi, K. H. Lee, B. S. Kim, N. M. Cho, S. B. Kim, D.-W. Kim, D. Park, and B.-I. Ryu et al., "A 4-bit double SONOS memory (DSM) with 4 storage nodes per cell for ultimate multi-bit operation," in VLSI Tech. Dig., 2006, pp. 50-51.
8. J.-G. Yun, Y. Kim, I. H. Park, J. H. Lee, S. Kang, D.-H. Lee, S. Cho, D.-H. Kim, G. S. Lee, W.-B. Sim, Y. Son, H. Shin, J. D. Lee, and B.-G. Park, "Fabrication and characterization of fin SONOS flash memory with separated double-gate structure," Solid-State Electron., vol.52, pp. 1498-1504, 2008.
9. E. Lusky, S.D.Yosi, G. Mitenberg,A. Shappir, I. Bloom, and B. Eitan, "Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices," IEEE Trans. Electron Devices, vol.51, no.3, pp. 444-451, Mar. 2004.
10. International Technology Roadmap for Semiconductor, Semiconductor Ind. Assoc., San Jose, CA, 2005.
11. H.-T. Lue, T.-H. Hsu, M.-T. Wu, K.-Y. Hsieh, R. Liu, and C.-Y. Lu, "Studies of the reverse read method and second-bit effect of 2-bit/cell nitride trapping device by quasi-two-dimensional mode," IEEE Trans. Electron Devices, vol.53, no.1, pp. 119-125, Jan. 2006.
12. C.W. Oh,N.Y.Kim, S.H.Kim,Y. L.Choi, S. I.Hong, H. J. Bae, J. B. Kim, K. S. Lee, Y. S. Lee, N. M. Cho, D.-W. Kim, D. Park, and B.-I. Ryu, "4-bit double SONOS memories (DSMs) using single-level and multi-level cell schemes," in IEDM Tech. Dig., 2006, pp. 1-4.
13. H. Cho, P. Kapur, P. Kalavade, and K. C. Saraswat, "Highly scalable vertical double gate NOR flash memory," in IEDM Tech. Dig., 2007, pp. 917-918.
14. R. Huang, F. Zhou, Y. Li, Y. Cai, X. Shan, X. Zhang, and Y.Wang, "Novel silicon-based flash cell structures for low power and high density memory applications," in Proc. ICSICT, Oct. 2006, pp. 709-712.
15. Y. Kim, J.-G. Yun, I. H. Park, S. Cho, J. H. Lee, S.-H. Park, D. H. Lee, D.-H. Kim, G. S. Lee, W. B. Sim, J. D. Lee, and B.-G. Park, " Locallyseparated vertical channel SONOS flash memory (LSVC SONOS) for multi-storage and multi-level operation," presented at the IEEE Silicon Nanoelectron. Workshop, Honolulu, HI, 2008, IEEE Paper P2-33.
16. S. Cho, I. H. Park, J. H. Lee, J.-G. Yun, D.-H. Kim, J. D. Lee, H. Shin, and B.-G. Park, "Establishing read operation bias schemes for 3-D pillar structure flash memory devices to overcome paired cell interference (PCI)," IEICE Trans. Electron., vol.E91-C, no.5, pp. 731-735, May 2008.
17. C. Lombardi, S.Manzini, A. Saporito, and M. Vanzi, "A physically based mobility model for numerical simulation of nonplanar devices," IEEE Trans. Comput. Aided Des., vol.7, no.11, pp. 1164-1171, Nov. 1988.
18. J.-W. Han, J. Lee, D. Park, and Y.-K. Choi, "Body thickness dependence of impact ionization in a multiple-gate FinFET," IEEE Electron Device Lett., vol.28, no.7, pp. 625-627, Jul. 2007.